[Show abstract][Hide abstract] ABSTRACT: We report a new NBTI phenomenon for p-MOSFETs with ultra thin gate oxides. We demonstrate that in a CMOS inverter circuit, the interface traps generated under NBTI stressing in a p-MOSFET (corresponding to the "high" output state of the inverter) are subsequently passivated when the gate to drain voltage switches to positive (corresponding to the "low" output state of the inverter). As a result, it was found that this "Dynamic" NBTI (DNBTI) operating in a CMOS inverter circuit prolongs significantly the device lifetime while the conventional "static" NBTI (SNBTI) underestimates the device lifetime. Furthermore, the DNBTI effect is dependent on temperature and gate oxide thickness, but independent of operation frequency. A physical model is proposed for DNBTI that involves the interaction between hydrogen and silicon dangling bonds. This finding has significant impact on the determination of maximum operation voltage as well as lifetime projection for future scaling of CMOS devices.
[Show abstract][Hide abstract] ABSTRACT: For the first time, a dynamic negative bias temperature instability (DNBTI) effect in p-MOSFETs with ultrathin gate oxide (1.3 nm) has been studied. The interface traps generated under NBTI stressing corresponding to p-MOSFET operating condition of the "high" output state in a CMOS inverter, are subsequently passivated when the gate to drain voltage switches to positive corresponding to the p-MOSFET operating condition of the "low" output state in the CMOS inverter. Consequently, this DNBTI effect significantly prolongs the lifetime of p-MOSFETs operating in a digital circuit, and the conventional static NBTI (SNBTI) measurement underestimates the p-MOSFET lifetime. A physical model is presented to explain the DNBTI. This finding has significant impact on future scaling of CMOS devices.
IEEE Electron Device Letters 01/2003; · 2.79 Impact Factor
[Show abstract][Hide abstract] ABSTRACT: The effect of high nitrogen concentration incorporation using decoupled plasma nitridation (DPN) of ultra-thin gate oxide (≈15–17 Å) on p-channel MOSFET performance has been investigated and compared with the conventional thermal nitridation process. Boron penetration is successfully suppressed in the ultra-thin gate dielectric prepared by the DPN process. This is confirmed by the measurements of gate leakage current, flat-band voltage shift and interface trap densities. The success in blocking boron penetration by DPN is attributed to its capability in incorporating a high level of nitrogen to near the top interface of the gate oxide. However, as a result of high level nitridation by DPN, a degradation in transconductance (Gm) is observed and interface trap density is also increased, compared to the conventional thermal nitridation process.
Semiconductor Science and Technology 05/2002; 17(6):L25. · 1.92 Impact Factor
[Show abstract][Hide abstract] ABSTRACT: The degradation of 0.13μm NMOS and PMOS transistors caused by microtrenching (μT) under hot-carrier and edge FN stress is studied. DAHC stress was found to be a sensitive technique for characterizing the NMOS transistors while edge FN stress was more suitable for the PMOS transistors. Interface state generation was also identified as the dominant degradation mechanism.
Plasma- and Process-Induced Damage, 2002 7th International Symposium on; 02/2002
[Show abstract][Hide abstract] ABSTRACT: The impact of nitrogen plasma nitridation on the interfacial quality of ultrathin oxide (1.8 nm and 2.6 nm) and negative bias temperature instability (NBTI) have been investigated. It is found that the plasma-nitridation can more effectively suppress nitrogen-induced and boron-induced hole mobility degradation than that of thermal nitridation. Therefore, a higher amount of nitrogen can be incorporated into the plasma-nitrided oxide to suppress boron penetration without compromising the oxide interfacial quality. Furthermore, plasma-nitrided oxides have higher resistance to NBTI and longer NBTI-lifetime than that of thermal-nitrided oxides.
Physical and Failure Analysis of Integrated Circuits, 2002. IPFA 2002. Proceedings of the 9th International Symposium on the; 02/2002
[Show abstract][Hide abstract] ABSTRACT: The effects of postdeposition anneal of chemical vapor deposited silicon nitride are studied. The Si/sub 3/N/sub 4/ films were in situ annealed in either H/sub 2/(2%)/O/sub 2/ at 950/spl deg/C or N/sub 2/O at 950/spl deg/C in a rapid thermal oxidation system. It is found that an interfacial oxide was grown at the Si/sub 3/N/sub 4//Si interface by both postdeposition anneal conditions. This was confirmed by thickness measurement and X-ray photoelectronic spectroscopy (XPS) analysis. The devices with H/sub 2/(2%)/O/sub 2/ anneal exhibit a lower gate leakage current and improved reliability compared to that of N/sub 2/O anneal. This improvement is attributed to a greater efficiency of generating atomic oxygen in the presence of a small amount of hydrogen, leading to the elimination of structural defects in the as-deposited Si/sub 3/N/sub 4/ film by the atomic oxygen. Good drivability is also demonstrated on a 0.12 /spl mu/m n-MOSFET device.
IEEE Electron Device Letters 01/2002; 23:124-126. · 2.79 Impact Factor
[Show abstract][Hide abstract] ABSTRACT: The gate-controlled-diode (GCD) characteristic of a deep submicron MOSFET is changed dramatically following a Fowler–Nordheim (FN) injection. The changes can be explained by the trap generation on the Si surface close to the channel/drain edge and the interface trap generation in the channel region. By examining the change in the reverse drain current under accumulation and inversion in the GCD measurements, the information of trap generation in the surface region close to the channel/drain edge is obtained (note that the trap generation in this region could be different from that in other interface regions); and by measuring the reverse drain current under depletion, the interface trap generation in the channel region is obtained.
[Show abstract][Hide abstract] ABSTRACT: The effect of X-ray lithography (XRL) process on the reliability of thin gate oxide has been investigated. A large increase in the low-field excess leakage current was observed on irradiated oxides, which was very similar to the electrical stress-induced leakage currents. However, it has been found that the long-term reliability of ultra-thin gate oxide is not affected by XRL process. The excess leakage current could be eliminated by thermal annealing at 400°C and above and no residual damages in the oxide were observed after the annealing.
Japanese Journal of Applied Physics 01/2001; 40. · 1.07 Impact Factor
[Show abstract][Hide abstract] ABSTRACT: Low-field leakage currents in thin gate oxides can be induced by 10 keV x-ray irradiation and electrical stress. The characteristics of radiation-induced leakage current (RILC) and stress-induced leakage current (SILC) in thin oxides have been studied and compared. The characteristics of RILC are found to be very similar to SILC, indicating that both RILC and SILC have essentially the same conduction mechanism, and are contributed by common defects generated in the gate oxides during irradiation or electrical stress. In particular, it has been demonstrated that oxide-trapped holes contribute significantly to both RILC and SILC.
Semiconductor Science and Technology 09/2000; 15(10):961. · 1.92 Impact Factor
[Show abstract][Hide abstract] ABSTRACT: This paper presents the results of investigation on integrity of X-ray/E-beam irradiated thin gate oxides. A large increase of gate oxide leakage current is observed after irradiation on thin gate oxide under X-ray/E-beam lithography conditions. This radiation-induced leakage current (RILL) can be removed by a thermal annealing at 400°C and above, without adverse effect to the oxide integrity. In addition, it is found that ionizing exposures do not significantly affect the breakdown and quasi-breakdown characteristics in ultra-thin oxide.
[Show abstract][Hide abstract] ABSTRACT: Two components of the low-field current have been identified in
thin oxides, following 10 KeV X-ray irradiation. The first component,
observed in the direct tunneling region, can be removed by a 100°C
anneal, and is also greatly suppressed if the irradiation is done in
vacuum or in a nitrogen ambient, or if the oxide is preannealed before
irradiation. The origin of this current is speculated to be related to
adsorbed water molecules on the gate surface. The second component is
observed to begin in the pre-Fowler-Nordheim tunneling (FNT) region and
extends into the FNT region, only in oxides less than ~8 nm thick, and
persists even after several days of anneal at 300°C. This current
exhibits a power law dependence on radiation dose. The origin of this
second component is believed to be due to the trap-assisted tunneling
via neutral electron traps, similar to the leakage current observed in
the oxide after high-voltage stress
IEEE Transactions on Electron Devices 04/2000; · 2.06 Impact Factor
[Show abstract][Hide abstract] ABSTRACT: The carrier-separation characteristics of a p-channel metal-oxide-semiconductor field-effect transistor with 29 Å gate oxide has been measured at various temperatures from 90 to 375 K. It is found that the gate and source/drain currents at low gate voltage regime (below 0.5 V) were correlated and strongly dependent on temperature above 250 K. The earlier observation has been attributed to the existence of a temperature-sensitive hole direct-tunneling current due to the strong temperature sensitivity of surface hole's concentration at low voltage regime.
Journal of Applied Physics 01/2000; 88:2872-2876. · 2.21 Impact Factor