Are you B.T. Chen?

Claim your profile

Publications (6)0 Total impact

  • [Show abstract] [Hide abstract]
    ABSTRACT: Reliability concerns over the applications of porous low-k dielectrics for Cu dual damascene (DD) interconnects have been dismissed with novel film formation methods, patterning approaches and structure designs. Results showed that the BEOL time dependent dielectric breakdown (BEOL TDDB) performance of interconnects built using porous CVD LK's with k=2.2 and pore size ∼2.8nm were not comprised with film pore integrity retained to have TDDB T<sub>63</sub> predicted to be 1 × 10<sup>9</sup> yrs at 0.3 MV/cm and 125°C. Further investigations also revealed that the impacts of weak mechanical and poor thermal properties associated with the LK material on its interconnect electromigration and stress migration performances can be demolished through various interface engineering with EM lifetimes of 0.12 μm Cu lines or 0.13 μm vias at 1 MA/cm<sup>2</sup> and 110°C longer than 400k hrs or 150k hrs, and SM failure rate = 0 (>100% Re shift) for vias on all test structures after thermal annealing at 150°C for 500 hrs.
    VLSI Technology, 2004. Digest of Technical Papers. 2004 Symposium on; 07/2004
  • [Show abstract] [Hide abstract]
    ABSTRACT: Cu/porous low-k (PLK) with k≤2.5 is the current choice to 65nm and beyond BEOL interconnect technologies. However, critical concerns of the weak physical and chemical structures of PLK (k≤2.5) films on their integration compatibilities, such as CMP defectivity and trench bottom/via smoothness, electrical performances, such as etching/ashing film damaging, and reliability performances, such as electromigration (EM), stress migration (SM) and time-dependent dielectric breakdown (TDDB), still challenge their application feasibility. A novel in-situ formed trench-porous (k=2.5) and via-dense (k=2.7) k=2.5/2.7 bilayer film design was proposed in this study to overcome these facing issues. Cu/PLK DD study results showed that CMP defectivity was ∼4× improved and trench bottom was smoothened with a k=2.5/2,7 bilayer PLK approach. Electrical performances using this approach also showed that film damaging from DD etching/ashing was reduced with the higher chemical resistance of the via in the bilayer. Reliability study results demonstrated that an ∼ 2000× better DD TDDB lifetime was achieved due to smooth trench bottoms. When changing from Cu/k=2.5 single layer to Cu/k=2.5/2.7 bilayer, SM and EM performances were not impacted. Moreover, with >405 improved hardness and film adhesion the bilayer PLK approach highlights a potential direction to improve Cu/k=2.5 PLK manufacturability in packaging. All these results indicate that this Cu/bilayer BEOL interconnection applicable for 65 nm and beyond generation CMOS technologies.
    Interconnect Technology Conference, 2004. Proceedings of the IEEE 2004 International; 07/2004
  • [Show abstract] [Hide abstract]
    ABSTRACT: Successful integration of high performance Cu dual damascene interconnects (DDIs) using a low-k etch stop (LES, oxygen-doped carbide, k∼3.0) and a porous low-k IMD (OSG, k∼2.5) has been demonstrated for the first time. The Cu DDIs with the LES not only revealed excellent resistance to stress induced voiding (SIV) but also exhibited 21% better interconnect RC delay, 100% higher via-EM endurance, 100 times lower line-line leakage at 125°C, and 5% faster device operation speed as compared to the DDIs with a currently used etch stop (CES, oxygen-doped carbide, k∼4.5).
    Electron Devices Meeting, 2003. IEDM '03 Technical Digest. IEEE International; 01/2004
  • [Show abstract] [Hide abstract]
    ABSTRACT: Nine-metal-level (9 ML) Cu/CVD low-k dielectric with k=2.2, Cu/LK (k=2.2), damascene integration on 300 mm wafers for 90/65 nm generation has been successfully demonstrated for the first time. To minimize line-line capacitance for least BEOL interconnect RC delay, no higher-k cap for Cu CMP or higher-k middle etch stop layers for metal trench etching were used in inter metal dielectric (IMD) film stacking. Integration challenges in the Cu/LK (k=2.2) damascene building were overcome by novel approaches in IMD film processing, Cu CMP and patterning. Excellent physical, electrical, reliability, and packaging results from this Cu/LK (k=2.2) BEOL interconnects are demonstrated.
    VLSI Technology, 2003. Digest of Technical Papers. 2003 Symposium on; 07/2003
  • [Show abstract] [Hide abstract]
    ABSTRACT: Advanced metal barrier free (MBF) Cu dual damascene interconnects (DDIs) have been successfully fabricated using a low-k CVD OSG (k=2.5) and PECVD silicon carbides for the first time. With PECVD silicon carbides replacing TaN, the Cu DDIs thus built showed 8% better in interconnect RC delay, 36% lower in via resistance and three orders of magnitude lower in line-line leakage at 200/spl deg/C. The newly developed technology also enhanced Cu TDDB lifetime by more than three orders of magnitude. On the MBF DDIs, 15%-faster 90-nm CMOS device operation has been achieved, which makes the newly developed MBF Cu DDI technology promising for high performance sub-90 nm CMOS devices and beyond.
    Electron Devices Meeting, 2002. IEDM '02. International; 02/2002
  • [Show abstract] [Hide abstract]
    ABSTRACT: A spin-on dielectric (SOD, k=2.2) has been integrated with Cu for 0.10/0.07 μm generations. To minimize interconnect capacitance, conventional CVD cap layer (k=4.5-7.5) is replaced by a SOD dielectric (k=2.9) and no stop layer for trench etch is used for the porous inter-metal dielectric (IMD). The issue of photoresist poisoning is resolved by nitrogen-free IMD processing. Using polymeric abrasive together with polishing parameters designed in a low friction domain for planarization, 6-level Cu/porous SOD multilevel interconnect is demonstrated for the first time. Electrical testing shows promising results for the high-performance dual damascene structure.
    VLSI Technology, 2002. Digest of Technical Papers. 2002 Symposium on; 02/2002