[Show abstract][Hide abstract] ABSTRACT: In this study, the effect of Cluster Carbon implantation and thermal annealing for recrystallization on the properties of phosphorus doped Si (Si:P) epitaxial films was investigated. Several Cluster Carbon implantation conditions and recrystallization annealing techniques based on solid phase epitaxy with rapid thermal annealing (RTA), spike RTA (sRTA), and millisecond laser annealing have been employed. It was found that a high substitutional carbon concentration can be achieved by laser annealing while high thermal budget annealing caused the loss of almost half of the substitutional carbon. The reduction of end of range defects and stacking faults/dislocation loops at the surface of carbon and phosphorus doped Si (Si:CP) layers through the use of cold implantation and fewer implantations was confirmed. Although sRTA activates phosphorus, additional laser annealing improves phosphorus activation further in the Si:CP layer. The phosphorus profile is abrupt with Cluster Carbon implantation when compared to no carbon implantation.
Thin Solid Films 01/2014; 557:94–100. · 1.87 Impact Factor
[Show abstract][Hide abstract] ABSTRACT: Dual lens dark field electron holography and Moiré fringe mapping from dark field scanning transmission electron microscopy are used to map strain distributions at high spatial resolution in Si devices processed with stress memorization techniques (SMT). It provides experimental evidence that strain in the Si channel is generated by dislocations resulting from SMT. The highest value of strain, up to 1.1% (1.9 GPa in stress) occurs at the Si surface along the channel direction: ⟨110⟩. An increase of ∼0.2% strain in the channel is observed after removing the poly-Si gate through the replacement high-k metal gate process.
[Show abstract][Hide abstract] ABSTRACT: Dual lens operation for electron holography, which was developed previously (Wang et al., Ultramicroscopy 101 (2004) 63-72; US patent: 7,015,469 B2 (2006)), is re-investigated for bright field (junction profiling) and dark field (strain mapping) electron holography using FEI instrumentation (i.e. F20 and Titan). It is found that dual lens operation provides a wide operational range for electron holography. In addition, the dark field image tilt increases at high objective lens current to include Si 〈004〉 diffraction spot. Under the condition of high spatial resolution (1nm fringe spacing), a large field of view (450nm), and high fringe contrast (26%) with dual lens operation, a junction map is obtained and strain maps of Si device on 〈220〉 and 〈004〉 diffraction are acquired. In this paper, a fringe quality number, N', which is number of fringe times fringe contrast, is proposed to estimate the quality of an electron hologram and mathematical reasoning for the N' number is provided.
[Show abstract][Hide abstract] ABSTRACT: A thin body (fully depleted) strained SGOI device structure (FDSGOI), and a strained SiGe channel layer on SOI, were fabricated using scaled high-κ gate dielectrics and metal gate technology. The uniaxial strain effect and corresponding drive current enhancement reported by Irisawa et al.  for narrow-width devices was investigated on these structures. Although the strained FDSGOI device structure exhibited reduced off-state leakage compared to thicker body devices, and long-channel drive current enhancement under uniaxial strain, the loss of drive current enhancement at short channel length led to uncompetitive ION–IOFF characteristics. The SiGe on SOI structure showed the highest long-channel drive current enhancement (nearly 3×) in the narrowest devices, and also showed a significant reduction in off-state current. This trend was maintained down to the shortest channel lengths studied here and resulted in ION–IOFF characteristics that were competitive with contemporary uniaxial strained Si channel devices.
[Show abstract][Hide abstract] ABSTRACT: Three techniques based on transmission electron microscope (TEM) have been successfully applied to measure strain/stress in the channel area of PMOS semiconductor devices with embedded SiGe in the source/drain areas: convergent beam electron diffraction (CBED), nano beam diffraction (NBD) and dark-filed holography (DFH). Consistent channel strain measurements from the three techniques on the same TEM sample (eSiGe PMOS with 17%Ge) were obtained. Reliable strain/stress measurement results in the channel area have been achieved with very good agreement with computer-aided design (TCAD) calculations.
[Show abstract][Hide abstract] ABSTRACT: Instrumentation and Techniques SymposiaStrain Mapping on Semiconductor Device by Dark Field Electron HolographyArticle author querywang y [PubMed]
[Google Scholar]li j [PubMed]
[Google Scholar]bruley j [PubMed]
[Google Scholar]domenicucci a [PubMed]
[Google Scholar]cooper d [PubMed]
[Google Scholar]jean-luc r [PubMed]
[Google Scholar]YY Wanga1, J Lia1, J Bruleya1, A Domenicuccia1, D Coopera2 and R Jean-Luca2a1 IBM
[Show abstract][Hide abstract] ABSTRACT: Nano-beam diffraction (NBD) has been successfully used in measuring channel strain in device of embedded SiGe (eSiGe). Strain measurements have been correlated to different processing conditions and microstructures of eSiGe and device performance. For intrinsic eSiGe without growth defect with 15-17%Ge, the average channel strain measured by NBD is ~ -0.55%, consistent with our previous measurement by convergent electron beam diffraction (CBED) and TCAD simulation. For graded eSiGe with average ~22%Ge, the average channel strain measured by NBD is ~ -0.90%, which is lower than the TCAD simulation. Differences between experimental results and simulation are also discussed.
[Show abstract][Hide abstract] ABSTRACT: This paper presents for the first time (110) PMOS characteristics without R<sub>ext</sub> degradation, allowing investigation of fundamental mobility and demonstration of drive current I<sub>on</sub> in excess of 1mA/mum at I<sub>off</sub> =100 nA/mum.
Electron Devices Meeting, 2007. IEDM 2007. IEEE International; 01/2008
[Show abstract][Hide abstract] ABSTRACT: In this paper, we quantify the relation of low lateral electric field hole mobility and channel strain to the virtual source velocity of nanoscale p-type SOI MOSFET devices with effective channel length from 35 to 50 nm and show strong correlation. The mobility is modified by the application of uniaxial compressive strain in the I GPa regime to the channel by employing two stressors-(1) embedded SiGe (eSiGe) at the source/drain areas and (2) compressive strain silicon nitride contact liner film. The corresponding changes in low-field mobility and saturation drain current are significant.
Device Research Conference, 2007 65th Annual; 07/2007
[Show abstract][Hide abstract] ABSTRACT: Addition of Pt to Ni silicide produces a robust [Ni<sub>x</sub>Pt<sub>(1-x)</sub>]Si, which shows an improved morphological stability, an important reduction in encroachment defect density, a reduced tendency to form NiSi<sub>2</sub> and significant variations in monosilicide texture without degrading the device performance or the yield of high-performance 65 nm SOI technologies.
VLSI Technology, Systems and Applications, 2007. VLSI-TSA 2007. International Symposium on; 05/2007
[Show abstract][Hide abstract] ABSTRACT: A novel device structure containing a SiGe stressor is used to impose tensile strain in nMOSFET channel. 400MPa of uniaxial tensile stress is induced in the Si channel through elastic relaxation/strain of the SiGe/Si bi-layer structure. This strain results in 40% mobility enhancement and 15% drive current improvement for sub-60nm devices compared to the control device with no strain
Electron Devices Meeting, 2006. IEDM '06. International; 01/2007
[Show abstract][Hide abstract] ABSTRACT: We present a 45-nm SOI CMOS technology that features: i) aggressive ground-rule (GR) scaling enabled by 1.2NA/193nm immersion lithography, ii) high-performance FET response enabled by the integration of multiple advanced strain and activation techniques, iii) a functional SRAM with cell size of 0.37mum<sup>2</sup>, and iv) a porous low-k (k=2.4) dielectric for minimized back-end wiring delay. The list of FET-specific performance elements includes enhanced dual-stress liner (DSL), advanced eSiGe, stress memorization (SMT), and advanced anneal (AA). The resulting PFET/NFET Idsat values, at Vdd of 1.0V and 45nm GR gate pitch, are 840muA/mum and 1240muA/mum respectively. The global wiring delay achieved with k=2.4 reflects a 20% reduction compared to k=3.0
Electron Devices Meeting, 2006. IEDM '06. International; 01/2007
[Show abstract][Hide abstract] ABSTRACT: Implant damage and strain relaxation in thin epitaxial silicon germanium (SiGe) layers on silicon (Si) (001) and their dependence on in situ carbon (C) doping in epitaxial SiGe are studied. For a 65 nm SiGe layer with ∼ 25% germanium (Ge), conventional implants used for p-metal-oxide semiconductor source/drain, halo, and extension led to significant implant damage and strain relaxation. Two defect bands were observed, one close to the surface and the other at SiGe/Si interface. In situ C doping (1019–1020/cm3) was found to eliminate the implant damage close to SiGe/Si interface area and prevent significant strain relaxation.
[Show abstract][Hide abstract] ABSTRACT: A high performance 65 nm SOI CMOS technology is presented. Dual stress liner (DSL), embedded SiGe, and stress memorization techniques are utilized to enhance transistor speed. Advanced-low-K BEOL for this technology features 10 wiring levels with a novel K=2.75 film in selected levels. This film is a SiCOH-based dielectric optimized for stress to enable integration for enhanced performance. The resulting technology delivers pFET and nFET AC switching on-current of 735 muA/mum and 1259 muA/mum respectively, at an off-current of 200 nA/um (V<sub>dd</sub>=1.0 V), and 6% reduction in interconnect delay. Process yield is demonstrated on a SRAM cell with size of 0.65 mum<sub>2</sub>
Electron Devices Meeting, 2005. IEDM Technical Digest. IEEE International; 01/2006
[Show abstract][Hide abstract] ABSTRACT: Strain Engineering has become extremely important in the semiconductor industry as a means of achieving device performance
enhancement as device scaling runs out of steam. It is important to detect strain as a function of position in device sized
areas in order to assess the viability of different process schemes. In the present work, Moire fringe patterns were used
to measure and map the relaxation effects in SiGe and Si/SiGe structures fabricated on SIMOX substrates. Initially, measurements
of the strain state using the Moire technique were correlated with those obtained by x-ray diffraction for blanket SiGe on
insulator films over the range 0.2–0.8%. Using this correlation as a basis, several interesting relaxation characteristics
were found on patterned structures. Evidence of a rhombohedral relaxation was seen for rectangular SiGe mesas fabricated by
patterning and then homogenizing SiGe/Si bilayers on SIMOX substrates. The magnitude of the relaxation was found to depend
of the size of the structure and the distance to the nearest edge. Elastic relaxation of Si lines was also seen. Lastly, evidence
of non uniform relaxation was seen in the SiGe template in wide channel areas of silicide-contacted device structures.
[Show abstract][Hide abstract] ABSTRACT: A variable magnification electron holography, applicable for two-dimensional (2-D) potential mapping of semiconductor devices, employing a dual-lens imaging system is described. Imaging operation consists of a virtual image formed by the objective lens (OL) and a real image formed in a fixed imaging plane by the objective minilens. Wide variations in field of view (100-900 nm) and fringe spacing (0.7-6 nm) were obtained using a fixed biprism voltage by varying the total magnification of the dual OL system. The dual-lens system allows fringe width and spacing relative to the object to be varied roughly independently from the fringe contrast, resulting in enhanced resolution and sensitivity. The achievable fringe width and spacing cover the targets needed for devices in the semiconductor technology road map from the 350 to 45 nm node. Two-D potential maps for CMOS devices with 220 and 70 nm gate lengths were obtained.
[Show abstract][Hide abstract] ABSTRACT: Defects in strained Si layers grown on relaxed SiGe layers were studied using chemical etching and transmission electron microscopy. Defect densities were measured in strained Si layers formed on SiGe buffer layers grown on bulk Si, as well as silicon–germanium-on-insulator substrates. It is found that, in addition to threading dislocations and dislocation pile ups, stacking faults are present in nearly all of the materials studied. The stacking faults are shown to originate in the relaxed SiGe alloy suggesting that they form during the relaxation of the SiGe layer.