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ABSTRACT: We develop, for the first time, a compact and scalable model to account for the poly-space effects (PSEs) in uniaxially-strained etch stop layer (ESL) stressors. The model is based on 2-dimensional (2D) finite element (FEM) stress simulations and 4-point bending characterization of silicon, and agrees well with measured data. The impact of PSEs on circuit performance is also discussed.
SOI Conference, 2007 IEEE International; 11/2007
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P. Grudowski,
V. Dhandapani,
S. Zollner,
D. Goedeke,
K. Loiko,
D. Tekleab,
V. Adams,
G. Spencer,
H. Desjardins,
L. Prabhu,
R. Garcia, M. Foisy,
D. Theodore,
M. Bauer,
D. Weeks,
S. Thomas,
A. Thean,
B. White
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ABSTRACT: We report a CMOS-compatible embedded silicon-carbon (eSiC) source/drain stressor technology with NMOS performance enhancement. The integration includes up to 2.6% substitutional carbon (C<sub>sub</sub>) epitaxial Si:C and laser spike annealing (LSA) for increased C<sub>sub</sub> incorporation. 26% channel resistance (Rch) reduction and 11% Idlin-Ioff enhancement for 0.5% C<sub>sub</sub> and 60% Rch reduction for 2.2% C<sub>sub</sub> are demonstrated.
SOI Conference, 2007 IEEE International; 11/2007
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ABSTRACT: Thin SiGe-channel confinement is found to provide significant control of the short channel effects typically associated with nonbandedge gate electrodes, in an analogous manner to ultrathin-body approaches. Gate workfunction requirements for thin-SiGe-channel p-type field effect transistors are therefore relaxed substantially more than what is expected from a simple observation of the difference between gate and channel workfunctions. In particular, thin-SiGe channels are shown to enable cost-effective high-performance bulk CMOS technologies with a single gate workfunction near the conduction bandedge. Buried channel, gate workfunction, metal gate, SiGe-channel confinement effects, SiGe-channel MOSFET, silicon germanium, ultrathin-body (UTB).
IEEE Electron Device Letters 09/2007; · 2.85 Impact Factor
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Xiang-Zheng Bo,
P. Grudowski,
V. Adams,
K. Loiko,
D. Tekleab,
S. Filipiak,
J. Hackenberg,
V. Kolagunta, M. Foisy,
Li-Te Lin,
K.H. Fung,
Chi-Hsi Wu,
Hsiao-Chin Tuan,
J. Cheek
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ABSTRACT: We report on the optimized transverse and lateral boundaries of dual etch stop layer (dESL) stressors in both PMOS and NMOS achieved in 65nm SOI transistors. We demonstrate that this gives an additional ~20% performance gain in ring oscillators. The optimization takes into account the 1-D and 2-D geometry effects, including poly-pitch, and is in good agreement with stress simulations
International SOI Conference, 2006 IEEE; 11/2006
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D. Zhang,
B.Y. Nguyen,
T. White,
B. Goolsby,
T. Nguyen,
V. Dhandapani,
J. Hildreth, M. Foisy,
V. Adams,
Y. Shiho, [......],
C. Werkhoven,
H. Kirby,
C.H. Chang,
C.T. Lin,
H.C. Tuan,
Y.C. See,
S. Venkatesan,
V. Kolagunta,
N. Cave,
J. Mogab
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ABSTRACT: We report for the first time PMOS drive current enhancement with in-situ boron doped SiGe incorporation in recessed S/D regions for devices built on thin body SOI substrate. For P-channel PD-SOI devices with 450 A silicon on insulator and 38nm gate length, 35% linear drain current enhancement and 20% saturation drain current improvement have been achieved with this approach. Device integration and performance improvement are discussed below.
VLSI Technology, 2005. Digest of Technical Papers. 2005 Symposium on; 07/2005
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ABSTRACT: The recess of silicon in the source/drain and extension area severely compromises the performance of sub-50 nm MOSFETs. In this paper we investigate the influence of silicon recess on the transistor characteristics using process and device simulation, and systematically map the engineering space for optimization of channel, halo, S/D implants, spacer formations, silicidation and integration schemes to mitigate the silicon surface gouging using response surface modeling.
Simulation of Semiconductor Processes and Devices, 2003. SISPAD 2003. International Conference on; 10/2003
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G.C.-F. Yeap,
J. Chen,
P. Grudowski,
Y. Jeon,
Y. Shiho,
W. Qi,
S. Jallepalli,
N. Ramani,
K. Hellig,
L. Vishnubhotla, [......],
D. Burnett,
P. Ingersoll,
K. Wimmer,
S. Veeraraghavan, M. Foisy,
M. Hall,
J. Pellerin,
D. Wristers,
M. Woo,
C. Lage
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ABSTRACT: We report a 100 nm modular bulk CMOS technology platform with multi Vt and multi gate oxide integrated transistors that enables device and circuit co-design (M. Fukuma et al., VLSI Tech., 2000) techniques (e.g. well biasing and power down/reduction) for low standby power (LSP), high performance (HP), high speed (HS), and RF/analog system on chip (SoC) applications. The transistor performances are comparable to or better than recently reported data at the 100 nm technology node. This technology also features an all-layer copper/low-k (<3.0) interlayer dielectric (ILD) backend for speed improvement and dynamic power reduction (S. Parihar et al., Proc. IEDM, 2001).
VLSI Technology, 2002. Digest of Technical Papers. 2002 Symposium on; 02/2002
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ABSTRACT: The conventional I<sub>Dsat</sub>-I<sub>DL</sub> (where I<sub>Dsat
</sub> is drain current for V<sub>DS</sub>=V<sub>GS</sub>=V<sub>DD</sub>
with V<sub>BS</sub>=0, and I<sub>DL</sub> is drain current for V<sub>DS
</sub>=V<sub>DD</sub>, with V<sub>GS</sub>=V<sub>BS</sub>=0) curve falls
short in predicting which of two technology options will result in the
best circuit performance. Here, for the first time, we demonstrate an
improved evaluation method which accounts for process variation and
leakage current budgeting for a target gate length. By using iteration
or interpolation to compare tuned technologies, and by evaluating
leakage and drive currents from the appropriate portions of their
distribution curves, more effective optimization is achieved, giving
stronger weight to robust device design
Simulation of Semiconductor Processes and Devices, 2000. SISPAD 2000. 2000 International Conference on; 02/2000
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ABSTRACT: We discuss challenges particular to SOI simulation. We also show
evidence of what we believe is hot carrier diffusion out of the channel
near the drain, giving rise to a negative differential conductivity
(NDC), or a transient region in an I<sub>D</sub>-V<sub>D</sub> curve on
SOI
Simulation of Semiconductor Processes and Devices, 2000. SISPAD 2000. 2000 International Conference on; 02/2000
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ABSTRACT: We present a MOSFET design approach that contains a comprehensive
analytic representation of an advanced MOSFET structure and doping
profile. A methodology to extract parameters for the analytic
representation based on device simulation and IV and CV measurements is
described. The extracted model is scaled to sub-nominal dimensions to
illustrate its ability to predict device characteristics
Electron Devices Meeting, 1997. IEDM '97. Technical Digest., International; 01/1998
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ABSTRACT: Halo implants with various tilt angles and energies were compared from the point of hot carrier reliability. Our study shows that a larger tilt or a deeper, more energetic halo implant leads to stronger reverse short channel effects and higher electric field in the extension/channel junction. However, the net impact of a sharper extension/channel junction on hot carrier degradation was found to be minimal, because the weaker halo devices have higher substrate current resulting from higher drain currents which counterbalances increased electric field in the extension-channel junction for the stronger halo devices. However, when devices from two lots with similar performance parametrics, such as similar threshold voltage (V/sub t/) roll-off, were compared, larger tilt/lower energy halo devices were found to have less degradation than lower tilt/higher energy halos.
Reliability Physics Symposium Proceedings, 1998. 36th Annual. 1998 IEEE International;
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Jianan Yang,
Byoung Min,
S. Yasuhito,
Laegu Kang,
P. Walker,
M. Mendicino,
G. Yeap, M. Foisy,
K. Cox,
J. Cartwright,
S. Venkatesan
[show abstract]
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ABSTRACT: This paper describes how SOI film thickness affects performance and power consumption of a Partially-Depleted (PD) SOI microprocessor. System level speed/power performance will be compared directly between chips fabricated with different SOI film thickness. The performance improvement is also supported by device level and macro circuit level comparison. Yield issues associated with thinner SOI will also be addressed.
SOI Conference, 2003. IEEE International;
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L. Kang,
P. Grudowski,
Veer Dhandapani,
Yongjoo Jeon,
S. Goktepeli,
Byoung Min,
G. Yeap, M. Foisy,
S. Anderson,
M. Mendicino,
S. Venkatesan
[show abstract]
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ABSTRACT: Thinner Si body (700 Å) SOI CMOS was successfully demonstrated with spike RTA on 0.13 μm technology with 45 nm gate lengths and 16Å gate oxide. Spike RTA exhibited excellent short channel effect and lower miller capacitance (Cmiller), resulting in faster circuit speed and lower dynamic power compared to the conventional RTA. Spike RTA also showed comparable floating body effects and stress induced current degradation.
SOI Conference, 2003. IEEE International;
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P. Grudowski,
V. Adams,
Xiang-Zheng Bo,
K. Loiko,
S. Filipiak,
J. Hackenberg,
M. Jahanbani,
M. Azrak,
S. Goktepeli,
M. Shroff,
Wen-Jya Liang,
S.J. Lian,
V. Kolagunta,
N. Cave,
Chi-Hsi Wu, M. Foisy,
H.C. Tuan,
J. Cheek
[show abstract]
[hide abstract]
ABSTRACT: We report, for the first time, on the 2D boundary effects in a high performance 65nm SOI technology with dual etch stop layer (dESL) stressors. 1D geometry effects, such as poly pitch dependence, and the implications on SPICE models and circuit design are also discussed. It will be shown that PMOS and ring oscillator performance can be significantly enhanced by optimizing the transverse and lateral placement of the dESL boundary
VLSI Technology, 2006. Digest of Technical Papers. 2006 Symposium on;
