P. Abramowitz

Publications (9)2.85 Total impact

• Conference Proceeding: Realistic Projections of Product Fmax Shift and Statistics due to HCI and NBTI

  A. Haggag, M. Lemanski, G. Anderson, P. Abramowitz, M. Moosa
  [show abstract] [hide abstract]
  ABSTRACT: Product F_max shift is shown to be mainly due to HCI and NBTI. This is because the likelihood of a TDDB event in the product speed path is negligible. An exponential drain current and voltage dependence of HCI and a power-law gate voltage dependence of NBTI are shown to fit the F_max shift quite well for realistic guardbands.
  Reliability physics symposium, 2007. proceedings. 45th annual. ieee international; 05/2007
• Conference Proceeding: 65nm LP/GP mix low cost platform for multi-media wireless and consumer applications

  B. Tavel, B. Duriez, R. Gwoziecki, M.-T. Basso, C JULIEN, C. Ortolland, Y. Laplanche, R. Fox, E. Saboure, C. Detcheverry, [......], M. Marin, S. Boret, D. Gloria, S. Vanbergue, P. Abramowitz, L. Vishnubhotla, D. Reber, P. Stolk, M Woo, F. Arnaud
  [show abstract] [hide abstract]
  ABSTRACT: A complete 65nm CMOS platform, called LP/GP mix, has been developed employing thick oxide transistor (1.0), low power (LP) and general purpose (GP) devices on the same chip. Dedicated to wireless multi-media and consumer applications, this new triple gate oxide platform is low cost (+mask only) and saves over 35% of dynamic power with the use of the low operating voltage GP. The LP/GP mix shows competitive digital performance with a ring oscillator (FO=1) speed equal to 7ps per stage (GP) and 6T-SRAM static power lower than 1 Op A/cell (LP). Compatible with mixed-signal design requirements, transistors show high voltage gain, low mismatch factor and low flicker noise. Moreover, to address mobile phone demands, excellent RF performance has been achieved with F_T=160GHz for LP nMOS transistors.
  Solid-State Device Research Conference, 2005. ESSDERC 2005. Proceedings of 35th European; 10/2005
• Conference Proceeding: Ultra-thin gate dielectric reliability projections

  M. Moosa, A. Haggag, N. Liu, S. Kalpat, M. Kuffler, D. Menke, P. Abramowitz, M.E. Ramon, H.H. Tseng, T.Y. Luo, [......], J. Jiang, B.W. Min, C. Weintraub, J. Chen, S. Wong, C. Paquette, G. Anderson, P.J. Tobin, B.E. White Jr, M. Mendicino
  [show abstract] [hide abstract]
  ABSTRACT: Phenomenological time-dependent dielectric breakdown (TDDB) and bias-temperature instability (BTI) models are demonstrated to enable reasonably accurate reliability projections for several generations of silicon oxynitride-based transistors and circuits with EOT down to ∼1.3 nm. Furthermore, while reliability and performance can be traded-off by engineering the gate dielectric coupled with device integration, benchmarking of published data suggests that the reliability achievable at each transistor node falls within an intrinsically plausible range for similar dielectric films. A preliminary investigation of high-k dielectric device reliability suggests that a similar methodology can be adopted to project the reliability of scaled high-k films.
  Integrated Circuit Design and Technology, 2005. ICICDT 2005. 2005 International Conference on; 06/2005
• Conference Proceeding: Mechanism of Gm degradation and comparison of Vt instability and reliability of HfO2, HfSiOx and HfAlOx gate dielectrics with 80 nm poly-Si gate CMOS

  H.-H. Tseng, J.M. Grant, C. Hobbs, P.J. Tobin, L. Hebert, M. Ramon, S. Kalpat, F. Wang, D. Triyoso, D.C. Gilmer, B.E. White, P. Abramowitz, M. Moosa, Z. Luo, T.P. Ma
  [show abstract] [hide abstract]
  ABSTRACT: To achieve a lower gate leakage in high speed devices at the same equivalent oxide thickness, a major thrust is to replace the SiO₂ with a thicker dielectric that has a higher dielectric constant. Recently, there has been much interest in hafnium dioxide as a potential high-k gate dielectric as presented in E. P Gusev et a. (2001), B. Barlage et al. (2001), G. Wilk et al. (2001), C. Hobbs et al. (2001), W. Zhu et al. (2001), W. Qi et al. (2000) and B. Lee et al. (1999) due to its high permittivity. However, the polycrystalline microstructure may be undesirable. In order to increase the crystallization temperature, SiO₂ or Al₂O₃ are added to HfO₂ to form Hf silicates atid Hf aluminates. A systematic study to compare the device characteristics of these three major candidates is needed. In this work, we have compared them in terms of the key challenges of high-K devices such as Gm degradation, Vt instability, and reliability, in devices fabricated with a conventional CMOS process technology according to A. Perera et al. (2000).
  VLSI Technology, 2005. (VLSI-TSA-Tech). 2005 IEEE VLSI-TSA International Symposium on; 05/2005
• Article: Ultra-thin decoupled plasma nitridation (DPN) oxynitride gate dielectric for 80-nm advanced technology

  H.-H. Tseng, Y. Jeon, P. Abramowitz, T.-Y. Luo, L. Hebert, J.J. Lee, J. Jiang, P.J. Tobin, G.C.F. Yeap, M. Moosa, J. Alvis, S.G.H. Anderson, N. Cave, T.C. Chua, A. Hegedus, G. Miner, J. Jeon, A. Sultan
  [show abstract] [hide abstract]
  ABSTRACT: Balancing gate leakage reduction, device performance, and gate dielectric reliability is a major challenge for oxynitride used as a gate dielectric for advanced technology. As compared to RTONO oxynitride, pMOSFET threshold voltage shift and transconductance degradation have been problematic for devices using remote plasma nitridation (RPN) or decoupled plasma nitridation (DPN) process due to non-optimal nitrogen profile in the film. In this paper, we report that the nitrogen profile of DPN gate dielectric can be engineered primarily by tuning the plasma pressure after optimizing other DPN process parameters to solve these problems. An EOT of 15 /spl Aring/ (23-/spl Aring/ NMOS CETinv) DPN oxynitride is demonstrated to have an acceptable pMOS Vt, comparable transconductance, significantly (/spl sim/30/spl times/) longer pMOS time-to-breakdown reliability for packaged devices, and 5/spl times/ gate leakage reduction relative to a high quality RTONO used in industry. The high quality ultrathin DPN film is fabricated in a commercially available system, which is compatible with standard CMOS processing technology. These encouraging results make high-pressure DPN oxynitride an attractive gate dielectric candidate for 80-nm advanced technology and beyond.
  IEEE Electron Device Letters 01/2003; · 2.85 Impact Factor
• Conference Proceeding: A 100 nm copper/low-k bulk CMOS technology with multi Vt and multi gate oxide integrated transistors for low standby power, high performance and RF/analog system on chip applications

  G.C.-F. Yeap, J. Chen, P. Grudowski, Y. Jeon, Y. Shiho, W. Qi, S. Jallepalli, N. Ramani, K. Hellig, L. Vishnubhotla, [......], D. Burnett, P. Ingersoll, K. Wimmer, S. Veeraraghavan, M. Foisy, M. Hall, J. Pellerin, D. Wristers, M. Woo, C. Lage
  [show abstract] [hide abstract]
  ABSTRACT: We report a 100 nm modular bulk CMOS technology platform with multi Vt and multi gate oxide integrated transistors that enables device and circuit co-design (M. Fukuma et al., VLSI Tech., 2000) techniques (e.g. well biasing and power down/reduction) for low standby power (LSP), high performance (HP), high speed (HS), and RF/analog system on chip (SoC) applications. The transistor performances are comparable to or better than recently reported data at the 100 nm technology node. This technology also features an all-layer copper/low-k (<3.0) interlayer dielectric (ILD) backend for speed improvement and dynamic power reduction (S. Parihar et al., Proc. IEDM, 2001).
  VLSI Technology, 2002. Digest of Technical Papers. 2002 Symposium on; 02/2002
• Conference Proceeding: Metal gate MOSFETs with HfO2 gate dielectric

  S.B. Samavedam, H.H. Tseng, P.J. Tobin, J. Mogab, S. Dakshina-Murthy, L.B. La, J. Smith, J. Schaeffer, M. Zavala, R. Martin, [......], M. Moosa, D.C. Gilmer, C. Hobbs, W.J. Taylor, J.M. Grant, R. Hegde, S. Bagchi, E. Luckowski, V. Arunachalam, M. Azrak
  [show abstract] [hide abstract]
  ABSTRACT: We report for the first time electrical characterization of HfO₂ p- and n-MOSFETs with CVD TiN and PVD TaSiN gates respectively fabricated using conventional CMOS integration. Their performance is compared to PVD TiN-gated HfO₂ and SiO₂ n- and p-MOSFETs. To understand the issues with metal gates on high K gate dielectrics, PVD TiN MOSFETs were extensively characterized. At 10 nA/μm leakage, 0.345 mA/μm drive current was obtained from PVD TiN/HfO₂ p-MOSFETs. HfO₂ n-MOSFETs with metal gates show about 10⁴ times reduction in gate leakage compared to poly/SiO₂ devices.
  VLSI Technology, 2002. Digest of Technical Papers. 2002 Symposium on; 02/2002
• Conference Proceeding: A 45 nm gate length high performance SOI transistor for 100 nm CMOS technology applications

  M. Celik, S. Krishnan, M. Fuselier, A. Wei, D. Wu, B. En, N. Cave, P. Abramowitz, Byoung Min, M. Pelella, [......], B. Taylor, Yongjoo Jeon, Wen-Jie Qi, Ruigang Li, J. Conner, G. Yeap, M. Woo, M. Mendicino, O. Karlsson, D. Wristers
  [show abstract] [hide abstract]
  ABSTRACT: In this report, a high performance silicon-on-insulator (SOI) transistor for the 100 nm CMOS technology node is presented. Partially depleted (PD) transistors were fabricated in a 1000 Å-thick silicon film with gate lengths down to 45 nm, using a 16 Å nitrided gate oxide. At an operating voltage of 1.2 V, self-heated drive currents of 940 μA/μm and 460 μA/μm were achieved at 20 nA/μm for NMOS and PMOS respectively. Floating body effects (FBE) were minimized by special diode junction engineering to achieve maximum overall performance. A measured median stage delay of 6 ps was achieved on an inverter-fan-out-1 ring oscillator at 1.3 V at a total N+P leakage of 30 nA/μm. The exceptional AC performance of this technology is among the highest reported in the literature at this low transistor leakage and operating voltage.
  VLSI Technology, 2002. Digest of Technical Papers. 2002 Symposium on; 02/2002
• Source

  Available from: freescale.com

  Conference Proceeding: Dual-metal gate CMOS with HfO2 gate dielectric

  S.B. Samavedam, L.B. La, J. Smith, S. Dakshina-Murthy, E. Luckowski, J. Schaeffer, M. Zavala, R. Martin, V. Dhandapani, D. Triyoso, [......], J. Mogab, C. Thomas, P. Abramowitz, M. Moosa, J. Conner, J. Jiang, V. Arunachalarn, M. Sadd, B.-Y. Nguyen, B. White
  [show abstract] [hide abstract]
  ABSTRACT: We report for the first time on a novel dual-metal gate CMOS integration on HfO/sub 2/ gate dielectric using TiN (PMOS) and TaSiN (NMOS) gate electrodes. Compared to a single metal integration, the dual-metal integration does not degrade gate leakage, mobility and charge trapping behavior. Promising preliminary TDDB data were obtained from dual-metal gate MOSFETs, while still delivering much improved gate leakage (10/sup 4/ - 10/sup 5/ X better than SiO/sub 2/).
  Electron Devices Meeting, 2002. IEDM '02. International; 02/2002