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P Calka,
E Martinez,
V Delaye,
D Lafond,
G Audoit,
D Mariolle,
N Chevalier,
H Grampeix,
C Cagli, V Jousseaume,
C Guedj
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ABSTRACT: Structural, chemical and electronic properties of electroforming in the TiN/HfO(2) system are investigated at the nanometre scale. Reversible resistive switching is achieved by biasing the metal oxide using conductive atomic force microscopy. An original method is implemented to localize and investigate the conductive region by combining focused ion beam, scanning spreading resistance microscopy and scanning transmission electron microscopy. Results clearly show the presence of a conductive filament extending over 20 nm. Its size and shape is mainly tuned by the corresponding HfO(2) crystalline grain. Oxygen vacancies together with localized states in the HfO(2) band gap are highlighted by electron energy loss spectroscopy. Oxygen depletion is seen mainly in the central part of the conductive filament along grain boundaries. This is associated with partial amorphization, in particular at both electrode/oxide interfaces. Our results are a direct confirmation of the filamentary conduction mechanism, showing that oxygen content modulation at the nanometre scale plays a major role in resistive switching.
Nanotechnology 02/2013; 24(8):085706. · 3.98 Impact Factor
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ABSTRACT: Metal/ HfO <sub>2</sub>/ Pt stacks (where the metal is Au, Ag, Co, Ni, Cr, or In) are voltage stressed to induce a high-to-low resistive transition. No current compliance is applied during stressing (except the 100 mA limit of the voltage source). As a consequence very high conductance states are reached after switching, similar to a hard breakdown. Samples conductance after breakdown can reach up to 0.1 S, depending on the metal electrode. Despite the high postbreakdown conductance level, the samples are able to recover an insulating state by further voltage biasing (“high current resistance switching”).
Applied Physics Letters 02/2011; · 3.84 Impact Factor
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C. Cagli,
J. Buckley, V. Jousseaume,
A. Salaun,
H. Grampeix,
J. F. Nodin,
H. Feldis,
A. Persico,
J. Cluzel,
P. Lorenzi,
L. Massari,
R. Rao,
F. Irrera,
T. Cabout,
A. Padovani,
O. Pirrotta,
L. Vandelli,
L. Larcher,
G. Reimbold,
B. de Salvo
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ABSTRACT: In this work, the impact of Ti electrodes on the electrical behaviour of HfO2-based RRAM devices is conclusively clarified. To this aim, devices with Pt, TiN and Ti electrodes have been fabricated (see Fig. 1). We first provide several experiments to clearly demonstrate that switching is driven by creation-disruption of a conductive filament. Thus, the role of TiN/Ti electrodes is explained and modeled based on the presence of HfOx interfacial layer underneath the electrode. In addition, Ti is found responsible to activate bipolar switching. Moreover, it strongly reduces forming and switching voltages with respect to Pt-Pt devices. Finally, it positively impacts on retention. To support and interpret our results we provide physico-chemical measurements, electrical characterization, ab-initio calculations and modeling.
IEEE International Electron Devices Meeting, Washington, Washington DC, USA; 01/2011
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ABSTRACT: This paper focuses on the properties of nanoporous SiOCH thin films deposited using a porogen approach by plasma enhanced chemical vapor deposition. The impact of deposition temperature, porogen loading and porogen removal treatment is investigated using Fourier transform infrared spectroscopy, solid-state nuclear magnetic resonance analysis, and electrical and mechanical measurements. This work shows that a higher deposition temperature allows limiting the film shrinkage during the porogen removal treatment and leads to the best compromise in term of electrical and mechanical properties. Beside, the effect of Si–O–C bonds on the enhancement of mechanical properties is promoted since a typical crosslinking mechanism is highlighted in case of ultraviolet curing.
Journal of Applied Physics 01/2011; · 2.17 Impact Factor
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ABSTRACT: Resistance switching in Cu/SiO2-based conductive-bridging random access memories is studied under voltage and current-driven modes. These two modes are used to study memory cycling and time-dependent switching. Voltage-current (V-I) cycles (logarithmic current ramp) are compared to I-V cycles (linear voltage ramp). The Off-On transition in V-I cycles is governed by device capacitance. The Off-On switching time (in the 10−1–103 s range) was studied under constant voltage and constant current stresses. The switching time varies as exp(V0/V) and as 1/I. Switching kinetics is discussed considering a Fowler–Nordheim tunneling injection law and a field-induced nucleation theory.
Applied Physics Letters 05/2010; 96(19):193502-193502-3. · 3.84 Impact Factor
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ABSTRACT: Resistance switching is studied in Au / HfO <sub>2</sub> (10 nm)/(Pt, TiN) devices, where HfO <sub>2</sub> is deposited by atomic layer deposition. The study is performed using different bias modes, i.e., a sweeping, a quasistatic and a static (constant voltage stress) mode. Instabilities are reported in several circumstances (change in bias polarity, modification of the bottom electrode, and increase in temperature). The constant voltage stress mode allows extracting parameters related to the switching kinetics. This mode also reveals random fluctuations between the ON and OFF states. The dynamics of resistance switching is discussed along a filamentary model which implies oxygen vacancies diffusion. The rf properties of the ON and OFF states are also presented (impedance spectroscopy).
Journal of Applied Physics 05/2010; · 2.17 Impact Factor
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ABSTRACT: Pt/NiO-based devices are promising candidates for the next generation of resistive random access memories (RRAMs). X-ray (XPS) and ultraviolet (UPS) photoemission are performed to investigate the chemical and electronic properties of this stack. After resistive switching of the nickel oxide, the as-deposited and switched areas are compared in situ. The surface of the conductive area is characterised by a higher oxygen content as well as an enhancement of Ni3+ oxidation state, which can be related to defects such as Ni vacancies. The results are compatible with a bias-induced diffusion of O2− towards the anode, and a migration of Ni2+ towards the cathode. The NiO electron affinity is estimated to be 1.6 eV by UPS in the OFF state, leading to a Pt/NiO barrier height of 3.6 eV. Copyright © 2010 John Wiley & Sons, Ltd.
Surface and Interface Analysis 03/2010; 42(6‐7):783 - 786. · 1.18 Impact Factor
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V. Jousseaume,
J. Buckley,
Y. Bernard,
P. Gonon,
C. Vallee,
M. Mougenot,
H. Feldis,
S. Minoret,
G. Chamiot-Maitral,
A. Persico,
A. Zenasni,
M. Gely,
J.P. Barnes,
E. Martinez,
H. Grampeix,
C. Guedj,
J.F. Nodin,
B. De Salvo
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ABSTRACT: This work deals with the development of resistive memories based on oxides and their integration into the interconnection levels. The paper is focused on the screening of different dielectric oxides (metallic or not) showing resistive switching properties in order to lead to the highest performance resistive memories. Nickel oxide which is the most studied material in the literature is compared to other binary metallic oxides. In parallel, cells with silicon based dielectrics and Cu electrodes were developed. Electrical results allowed a comparison between the 3 main mechanisms observed in resistive memories based on oxides. Moreover, a specific resist flowing process and ion beam etching were optimized in order to limit metallic residues on memory cell side walls and prevent short-circuiting.
Interconnect Technology Conference, 2009. IITC 2009. IEEE International; 07/2009
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V. Arnal,
A. Farcy,
M. Aimadeddine, V. Jousseaume,
L.G. Gosset,
J. Guillan,
M. Assous,
L. Favennec,
A. Zenasni,
T. David,
K. Hamioud,
L.-L. Chapelon,
N. Jourdan,
T. Vanypre,
T. Mourier,
P. Chausse,
S. Maitrejean,
C. Guedj,
J. Torres
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ABSTRACT: Integrated circuits are more and more impacted by interconnect performance. As size reaches nanometric dimensions, changes in materials aim at performing a reliable and compliant technology with a maximum capability to reduce delay time and power consumption. At the 32 nm node, k value reduction of existing porous SiOCH and optimization of metallization with thin barrier, conformal seed and plating should mitigate RC and offer an improvement compared to current materials of the 45 nm node.
International Interconnect Technology Conference, IEEE 2007; 07/2007
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M. Aimadeddine, V. Jousseaume,
V. Amal,
L. Favennec,
A. Farcy,
A. Zenasni,
M. Assous,
M. Vilmay,
S. Jullian,
P. Maury, [......],
G. Imbert,
Y. LeFriec,
M. Mellier,
H. Chaabouni,
L.L. Chapelon,
K. Hamioud,
F. Volpi,
D. Louis,
G. Passemard,
J. Torres
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ABSTRACT: An Ultra Low-K (ULK) SiOCH porous dielectric with k=2.3 targeted for the 32 nm node is integrated at local and intermediate levels with the Trench First Hard Mask architecture currently implemented for the 65/45 nm nodes. Physical and electrical characterizations after integration show good barrier integrity, substantial gain in capacitance as well as good via chain functionality. The material exhibits similar interline leakage and breakdown field than the k=2.5 reference dielectric meeting specifications of the 32 nm node.
International Interconnect Technology Conference, IEEE 2007; 07/2007
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ABSTRACT: This paper presents a new a-SiC:H copper barrier deposited by PECVD using a precursor containing a phenyl group. Dielectric constant as low as 3.2 can be obtained by conserving phenyl cycles in the thin film. Material optimisation was performed in order to obtain both low k and Cu diffusion barrier behaviours. The optimized a-SiC:H was successfully integrated in a one metal level damascene interconnection as dielectric hard-mask and etch stop layers
Interconnect Technology Conference, 2006 International; 07/2006
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ABSTRACT: Conventional Cu-ultra low K (ULK) integration schemes lead to a drastic increase of the effective dielectric constant due to porous material degradation during process steps. Although a postintegration porogen removal scheme allows overcoming these issues, only spin-on dielectrics were developed to validate this approach. In this letter, plasma-enhanced chemical-vapor deposition is used to deposit ULK dielectric (k<2.5). The precursor chemistry and the deposition conditions have been chosen to obtain a material with the required characteristics to use a postintegration porogen removal approach: porogen thermal stability up to 325 °C, good mechanical properties of the hybrid film, no metallic barrier diffusion in the film, and a minimal shrinkage after the porogen removal treatment.
Applied Physics Letters 05/2006; 88(18):182908-182908-3. · 3.84 Impact Factor
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V. Jousseaume,
M. Assous,
A. Zenasni,
S. Maitrejean,
B. Remiat,
P. Leduc,
H. Trouve,
C. Le Cornec,
M. Fayolle,
A. Roule, [......],
A. Roman,
D. Scevola,
T. Morel,
D. Rebiscoul,
G. Prokopowicz,
M. Jackman,
C. Guedj,
D. Louis,
M. Gallagher,
G. Passemard
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ABSTRACT: Conventional Cu-ULK integration schemes lead to a drastic increase of the dielectric constant due to porous material degradation during process steps. In this paper, a post-integration porogen removal approach is studied to overcome this issue. Material optimization is presented (k=2.0) allowing the use of conventional BEOL integration processes such as oxygen-based etch chemistry, metal CVD barrier deposition and standard CMP process for dense low k. An integrated k value lower than 2.2 is obtained.
Interconnect Technology Conference, 2005. Proceedings of the IEEE 2005 International; 07/2005
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C. Guedj,
V. Arnal,
J.F. Guillaumond,
L. Arnaud,
J.P. Barnes,
A. Toffoli, V. Jousseaume,
A. Roule,
S. Maitrejean,
L.L. Chapelon,
G. Reimbold,
J. Torres,
G. Passemard
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ABSTRACT: With the scaling down of copper interconnects, the importance of interface engineering becomes more and more crucial. In this paper, we have studied the influence of the diffusion barriers on the electrical performance and dielectric reliability of porous ULK/Cu interconnects, in comparison with a reference dense SiCOH dielectric. The best reliability for the porous ULK is obtained with the thicker barrier, consisting of CVD TiN. With this barrier; the porous ULK can even outperform the dense dielectric in terms of time to failures and dielectric breakdown in certain cases. For the TaN barrier, an H<sub>2</sub> plasma after etch improves the breakdown voltage up to 34%. A voiding at the top Cu comers after storage in the 110°C-150°C range under N<sub>2</sub> has been identified as a possible contribution to the fracture of the SiCN top capping layer. Therefore the Cu itself is critical for the dielectric reliability.
Interconnect Technology Conference, 2005. Proceedings of the IEEE 2005 International; 07/2005
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ABSTRACT: In-situ friction characterization during chemical-mechanical polishing (CMP) was investigated to understand delamination mechanisms of a porous ultra low-k (ULK)/Cu stack. By quantifying the delaminated area within the wafer, it was shown that adhesion failure is driven by the work done against the CMP-induced friction force, and is correlated to the adhesion strength of the weakest interface. A low-stress CMP was successfully achieved on a first level of ULK/Cu interconnects having a low adhesion SiC/ULK interface (Gc=1.3 J/m<sup>2</sup>) and a porous dielectric material with low mechanical properties (Young's modulus E=3.5 GPa, hardness H=0.7 GPa).
Interconnect Technology Conference, 2005. Proceedings of the IEEE 2005 International; 07/2005
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R.J.O.M. Hoofman,
J. Michelon,
P.H.L. Bancken,
R. Daamen,
G.J.A.M. Verheijden,
V. Arnal,
O. Hinsinger,
L.G. Gosset,
A. Humbert,
W.F.A. Besling,
C. Goldberg,
R. Fox,
L. Michaelson,
C. Guedj,
J.F. Guillaumond, V. Jousseaume,
L. Arnaud,
D.J. Gravesteijn,
J. Torres,
G. Passemard
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ABSTRACT: The continuous downscaling of interconnect dimensions in combination with the introduction of porous low-k materials has increased the number of integration challenges tremendously. The paper focuses mainly on the impact of porous low-k dielectrics on interconnect reliability. Numerous reliability issues are induced by their porosity compared to dense low-k materials. The impact of these mechanically inferior materials on packaging is well known. However, on top of the mechanical reliability, ultra low-k materials are extremely vulnerable to processing (especially to plasmas), due to their inherent porosity. Additionally, it is difficult to deposit a continuous, thin barrier on porous low-k interfaces. The inferior properties of porous low-k materials as compared to their dense equivalents are thought to induce numerous reliability issues, which are in addition to the ones caused by the continuous downscaling of metal lines and dielectric spacings. All of this together has an enormous impact on the reliability of the end product.
Interconnect Technology Conference, 2005. Proceedings of the IEEE 2005 International; 07/2005
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ABSTRACT: The combination of porous ultra low k dielectric and copper metallization is an attractive alternative to meet the requirements of ITRS roadmap concerning the 65 nm interconnection technology, but very little is known about the reliability of such an approach. Porous materials are usually unstable and sensitive to moisture, but pore sealing is a possible strategy to overcome these detrimental effects. In this paper, we have studied the effect of pore sealing on the electrical performance and long-term reliability of ULK/Cu interconnects. The best pore sealing efficiency is obtained for a nominal thickness of 10 nm of a SiC:H sealing layer. With these conditions, the dielectric constant of the ULK is kept at 2.2 even after integration and an electromigration activation energy of 1.2 eV is obtained. The failures mechanisms have been correlated to SEM and FIB analysis.
Interconnect Technology Conference, 2004. Proceedings of the IEEE 2004 International; 07/2004
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ABSTRACT: This paper describes a new approach for optical interconnects, based on an above IC clock signal distribution with high compacity, using polymers with high refractive index difference. We investigate the design and its feasibility study and show the results on the first components obtained with similar materials. We demonstrate a high level of integration using materials compatible with microelectronic process, allowing an intra-chip optical distribution.
Interconnect Technology Conference, 2004. Proceedings of the IEEE 2004 International; 07/2004
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M. Fayolle, V. Jousseaume,
M. Assous,
E. Tabouret,
C. le Cornec,
P.H. Haumesser,
P. Leduc,
H. Feldis,
O. Louveau,
G. Passemard,
F. Fusalba
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ABSTRACT: This paper is focused on a new integration scheme to perform Cu/porous ULK interconnects. The dielectric (composite material made of porogen nano-particles dispersed in a MSQ matrix) is integrated in its non-porous state, preventing integration issues inherent in porous material. The porosity is only created after integration by a final thermal degradation of the porogen phase. Material, curing and processes compatibilities have been studied in order to perform single damascene interconnects. Electrical results prove the feasibility of this approach, showing that the porogen can be preserved during the integration and removed after the integration.
Interconnect Technology Conference, 2004. Proceedings of the IEEE 2004 International; 07/2004
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ABSTRACT: Supercritical CO<sub>2</sub> (SC CO<sub>2</sub>) processing was investigated for porous ultra low-k dielectric (ULK) and copper for successful Back End Of Line (BEOL) integration. The introduction of specific additives into a SC CO<sub>2</sub> and careful control of the process parameters lends this technique to a wide range of applications: 1. Stripping: Potentially able to replace both dry ash and wet clean steps to give a single fully compatible process for ULK/Cu. The main current limitation is the removal of resins hardened during dielectric etch. 2. Cleaning: SC CO<sub>2</sub> is a unique candidate for a dry-in/dry-out process able to clean surface and pores of ULK materials. The removal of Cu rich residues was demonstrated with a chelating agent dissolved in SC CO<sub>2</sub>. 3. Curing of ULK: Contamination by water and organics can significantly damaged ULK material and these can be eliminated by processing in SC CO<sub>2</sub>. Furthermore, by introducing a suitable additive, hexamethyldisilazane (HMDS), subsequent uptake of water was prevented.
Interconnect Technology Conference, 2003. Proceedings of the IEEE 2003 International; 07/2003
