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ABSTRACT: A system-on-chip integrating a microprocessor, three embedded FPGA (eFPGA) and an eight port network-on-chip (NoC) is implemented in a 90nm CMOS technology. The system has been designed to execute complex multimedia applications by the use of hardware accelerators mapped to a reconfigurable platform based on a message-passing architecture. Computational kernels are mapped as hardware autonomous processes inside the eFPGAs or locally accelerated by the usage of dedicated microprocessor coprocessors. Each eFPGA on the system can be independently programmed and share logic with the others eFPGAs by intra-communication channels. The architecture is highly scalable since the eFPGA number can be controlled and the reconfigurable platform communication channels are based on a configurable NoC. The silicon area required by the system is 26mm2 in a 90 nm CMOS process. 10x speed ups have been measured on a MP3 playler mapping example.
Field-Programmable Custom Computing Machines, 2005. FCCM 2005. 13th Annual IEEE Symposium on; 05/2005
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ABSTRACT: Application-specific standard products (ASSPs) have been so far customized by an increasing amount of embedded software or very recently by electrically and mask-programmable embedded gate-arrays. The solution proposed in this paper addresses both the large demand for higher flexibility and the need for fast product turn-around time. This is achieved by using single-via programmable logic and consistent hardware and software co-design flow. The system architecture is discussed as well as the design flows for pre- and post-silicon design and customization. The silicon area required by the system is 23 mm<sup>2</sup> in a 0.13 μm CMOS technology. The embedded via-programmable logic accounts for about 30% of the system area.
Custom Integrated Circuits Conference, 2004. Proceedings of the IEEE 2004; 11/2004
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ABSTRACT: A modified Flash-EEPROM device is presented. This device operates as a non-volatile programmable pass transistor. Program and erase, operations are performed on a Flash-EEPROM cell coupled to a pass-transistor. Written and erased states of the flash cell correspond to the open and close states of the pass-transistor respectively. The Flash-programmable pass transistor (FPT) was developed for multi-context programmable-logic, and it was realized in a technology for embedded Flash-EEPROM NOR memory. No additional process steps are required. This novel device has the same program and erasing behavior as the standard Flash-EEPROM cell, measurements are reported for a 0.18 μm technology implementation.
European Solid-State Device Research, 2003 33rd Conference on. ESSDERC '03; 10/2003
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ABSTRACT: A 1GOPS dynamically reconfigurable processing unit with embedded Flash memory and SRAM-based FPGA targets image-voice processing and recognition applications. Code, data, and FPGA bitstreams are stored in the embedded Flash memory and are independently accessible through 3 content-specific, 64-bit I/O ports with a peak read rate of 1.2GB/s. The system is implemented in a 0.18μm, 2PL-6ML CMOS Flash technology, chip area is 70mm<sup>2</sup>.
Design Automation Conference, 2003. Proceedings; 07/2003
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ABSTRACT: A system chip targeting image and voice processing and recognition application domains is implemented as a representative of the potential of using programmable logic in system design. It features an embedded reconfigurable processor built by joining a configurable and extensible processor core and an SRAM-based embedded field-programmable gate array (FPGA). Application-specific bus-mapped coprocessors and flexible input/output peripherals and interfaces can also be added and dynamically modified by reconfiguring the embedded FPGA. The architecture of the system is discussed as well as the design flows for pre- and post-silicon design and customization. The silicon area required by the system is 20 mm<sup>2</sup> in a 0.18-μm CMOS technology. The embedded FPGA accounts for about 40% of the system area.
IEEE Journal of Solid-State Circuits 04/2003; · 3.23 Impact Factor
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ABSTRACT: Consistency, accuracy and efficiency are key aspects for practical usability of a system design flow featuring automatic code generation. Consistency is the property of maintaining the same behaviour at different levels of abstraction through synthesis and refinement, leading to functionally correct implementation. Accuracy is the property of having a good estimation of system performances while evaluating a high-level representation of the system. Efficiency is the property of introducing low overheads and preserving performances at the implementation level. The RTOS is a key element of the link to implementation flow. In this paper, we capture relevant high-level RTOS parameters that allow consistency, accuracy and efficiency to be verified in a top-down approach. Results from performance estimation are compared against measurements on the actual implementation. Experimental results on automatically generated code show design flow consistency, an accuracy error of about 0.66% and an overhead of about 11.8% in term of speed.
Design, Automation and Test in Europe Conference and Exhibition, 2003; 02/2003
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ABSTRACT: A 1 GOPS dynamically reconfigurable processing unit with embedded flash memory and SRAM-based FPGA for image/voice processing/recognition applications is described. Code, data and FPGA bitstreams are stored in the embedded flash memory and are independently accessible through 3 content-specific, 64 b I/O ports with a peak read rate of 1.2 GB/s. The system is implemented in a 0.18 μm 2P 6M CMOS flash technology with a chip area of 70 mm<sup>2</sup>.
Solid-State Circuits Conference, 2003. Digest of Technical Papers. ISSCC. 2003 IEEE International; 02/2003
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ABSTRACT: A multi-context programmable on-chip communication network is implemented using a matrix of Flash-EEPROM pass-transistor switches (FPT) in a 0.18μm technology. The prototype 8-context, 8×8 64b crossbar includes 576k FPT and >8k bi-directional tristate repeaters in an area of 1.38mm<sup>2</sup>. Based on 2×2 building blocks, wave pipelining and elastic interconnect, data is transferred at 6.4Gb/s per channel, with independent clocks at both ends.
Solid-State Circuits Conference, 2003. Digest of Technical Papers. ISSCC. 2003 IEEE International; 02/2003
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ABSTRACT: The design of a single-chip, processor-based system with embedded built-in speech recognition capabilities is presented. The proposed system-on-chip is intended to be used for the implementation of autonomous embedded systems featuring voice control capabilities and command-oriented user interface. To allow a good flexibility of the recognition system and to achieve a single-chip system implementation, the main processing functionalities have been organized as co-processors and integrated around a 32-bit processor and a 2Mb embedded flash memory. The architecture of the system that features a recognition engine with a configurable data path is discussed. The silicon area required by the system is 25 mm<sup>2</sup>in a 0.18µm CMOS embedded flash technology.
Solid-State Circuits Conference, 2002. ESSCIRC 2002. Proceedings of the 28th European; 10/2002
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ABSTRACT: A system-chip targeting image and voice processing and recognition application domains is implemented as a representative of the potential of using programmable logic in system design. It features an embedded reconfigurable processor built by joining a configurable and extensible processor core and a SRAM-based embedded FPGA. Application-specific bus-mapped coprocessors and flexible I/O peripherals and interfaces can also be added and dynamically modified by reconfiguring the embedded FPGA. The architecture of the system is discussed as well as the design flows for pre- and post-silicon design and customisation. The silicon area required by the system is 20 mm<sup>2</sup> in a 0.18 μm CMOS technology. The embedded FPGA accounts for about 40% of the system area.
Custom Integrated Circuits Conference, 2002. Proceedings of the IEEE 2002; 02/2002
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ABSTRACT: A system-on-chip prototype implementing a full integration of a
64-minute digital voice recorder/player and embedding a 4-b/cell
multilevel digital flash memory is presented in this paper. A hardwired
adaptive-differential pulse-code modulation speech coder/decoder (8 to
40 kb/s) and a microcontroller are integrated into a bus-centric
architecture. An 8-Mcell/32-Mb multilevel flash memory is used as an
embedded mass storage media and a fully digital on-chip
built-in-self-test solution is presented. This speech recording system
features a modular architecture allowing full reuse and mix-and-match of
its IP building blocks. The architecture of the system and solutions for
implementing embedded multilevel flash memories are presented. System
operation modes are described showing how the desired message editing
functionality is implemented by a mixed hardware/software solution. The
chip is 3-V-only and it counts 13 M transistors at 225 mm<sup>2</sup>
area in a 0.5-μm embedded flash technology
IEEE Journal of Solid-State Circuits 04/2001; · 3.23 Impact Factor
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ABSTRACT: A system-on-chip prototype implements a full integration of a 64-minute digital voice recorder/player embedding a 4 bit/cell multilevel digital flash memory. A speech coder/decoder (8 to 40 kbps), an MCU and an 8 Mcell/32 Mb multilevel flash memory with fully digital on-chip BIST solution are integrated in a 0.5 μm embedded flash technology. The system features a modular architecture allowing full reuse and mix-and-match of its IP building blocks. The chip counts 13M transistors at 225 mm<sup>2</sup> area
Custom Integrated Circuits Conference, 2000. CICC. Proceedings of the IEEE 2000; 02/2000
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ABSTRACT: A 1GOPS dynamically reconfigurable processing unit with embedded Flash memory and SRAM-based FPGA targets image-voice processing and recognition applications. Code, data and FPGA bitstreams are stored in the embedded Flash memory and are independently accessible through 3 content-specific, 64-bit I/O ports with a peak read rate of 1.2GB/s. The system is implemented in a 0.18um, 2PL-6ML CMOS Flash technology, chip area is 70mm2.
