[Show abstract][Hide abstract] ABSTRACT: In this paper, we report on a modeling study of an AC electrothermal (ACET) micropump with
high operating pressures as well as fast flow rates. One specific application area is for fluid delivery
using microneedle arrays which require higher pressures and faster flow rates than have been
previously reported with ACET devices. ACET is very suitable for accurate actuation and control
of fluid flow, since the technique has been shown to be very effective in high conductivity fluids
and has the ability to create a pulsation free flow. However, AC electrokinetic pumps usually can
only generate low operating pressures of 1 to 100 Pa, where flow reversal is likely to occur with an
external load. In order to realize a high performance ACET micropump for continuous fluid
delivery, applying relatively high AC operating voltages (20 to 36 Vrms) to silicon substrate ACET
actuators and using long serpentine channel allows the boosting of operating pressure as well as
increasing the flow rates. Fast pumping flow rates (102–103 nl/s) and high operating pressures
(1–12 kPa) can be achieved by applying both methods, making them of significant importance for
continuous fluid delivery applications using microneedle arrays and other such biomedical devices.
Journal of Applied Physics 07/2013; 114(2). · 2.21 Impact Factor
[Show abstract][Hide abstract] ABSTRACT: Continuous valued number system is a novel number system which can be employed for developing analog signal processing units. It is a continuous number system which is represented by a set of continuous digits. One of the main features of this system is that digits share information, and have a digit-level redundancy. This redundancy is used to protect the digits against environment imperfections when implemented by analog circuits. In this paper, integrity of this number system in representing real values is explored. The study is required to show the effect of implementation imperfections which is an indicative of its feasibility. Effects of possible errors and error threshold for implementing this system are studied in this paper. An error recovery method is proposed, which enhances this number system representation. An efficient error recovery method extends the application of this number system in high density memory and storage devices for hardware implementations of neural networks.
Journal of Circuits System and Computers 04/2012; 20(08). · 0.33 Impact Factor
[Show abstract][Hide abstract] ABSTRACT: A high-swing, high-drive CMOS buffer amplifier, with good stability over a wide range of capacitive and resistive loads, is presented in this paper. A new area efficient output stage with a relatively small compensation capacitor has been used so that the circuit occupies only 120 mils2 in a 3 μm CMOS technology. The buffer has a drive capability of 110 kHz into a 5000 pF load with a rail-to-rail output swing for load resistances greater than 10 kΩ and acceptable total harmonic distortion with loads down to 270 Ω.
Journal of Circuits System and Computers 11/2011; 02(04). · 0.33 Impact Factor
[Show abstract][Hide abstract] ABSTRACT: Microneedles and microneedle arrays are capable of providing pathways for drug delivery or fluid extraction across the skin. Microneedles promise to impact health care by allowing the precise injection of therapeutic agents to prescribed locations below the skin. Since microneedles are capable of penetrating the stratum corneum (the first layer of skin) but not in penetrating deep enough into the dermis to cause noticeable pain, or are too small to significantly stimulate nerve endings, they are expected to provide almost painless
drug delivery. In this paper we report the progress in creating an integrated microneedle drug delivery system, from microneedle array design, fabrication and flow testing, through simulated transdermal fluid flow from the array, to controlled electrokinetic micropumping of fluids.
Canadian Congress of Applied Mechanics (CANCAM); 06/2011
[Show abstract][Hide abstract] ABSTRACT: This paper presents a novel camera simulation framework capable of simulating the optical path of a variety of camera systems through the technique of Monte Carlo Path tracing. Path tracer is a ray-tracing technique that uses Markov chains to solve the global illumination problem, i.e., the problem of calculating the distribution of light in an environment, taking into account all forms of scattering, absorption, and interreflection. In global illumination, we deal with the interaction of light that reaches a surface directly from a light source (direct lighting) as well as the interaction of light that reaches a surface as a result of scattering or transmission from or through other objects (indirect lighting). Available pieces of ray-tracer software use very simple models for their camera system like the pinhole camera, the thin-lens camera, and the thick-lens camera. The novelty and strength of our simulation tool is the capability to simulate any arbitrary and complex camera system. Any kind of optical component (like mirrors, prisms, and optical filters) can be placed inside the camera system or on the image sensor, and the tool synthesizes the image taken by that complex camera system, which can be used to optimize the parameters of the system for a specific application. The tool was used to simulate the optical path of a variety of passive depth recovery systems (like stereoscopy, Plenoptic Camera, and Bi-prism camera) that are included in this paper.
[Show abstract][Hide abstract] ABSTRACT: The ability to achieve fast fluid flow yet maintain a relatively low temperature rise is important for AC electrothermal (ACET) The ability to achieve fast fluid flow yet maintain a relatively low temperature rise is important for AC electrothermal (ACET)
micropumping, especially in applications such as bioMEMS and lab-on-a-chip systems. In this paper, we propose a two-phase micropumping, especially in applications such as bioMEMS and lab-on-a-chip systems. In this paper, we propose a two-phase
ACET fluidic micropump using a coplanar asymmetric electrode array. The proposed structure applies a two-phase AC voltage, ACET fluidic micropump using a coplanar asymmetric electrode array. The proposed structure applies a two-phase AC voltage,
i.e., voltage of phase 0°/180°, to the narrow electrodes while the wide electrodes are at ground potential. Numerical simulation i.e., voltage of phase 0°/180°, to the narrow electrodes while the wide electrodes are at ground potential. Numerical simulation
demonstrates that this simple coplanar electrode configuration can achieve at least 25% faster fluid flow rates than using demonstrates that this simple coplanar electrode configuration can achieve at least 25% faster fluid flow rates than using
a single AC signal. By selecting certain design parameters, a two-phase ACET structure can achieve up to 50% faster fluid a single AC signal. By selecting certain design parameters, a two-phase ACET structure can achieve up to 50% faster fluid
flow rates than a corresponding single-phase structure. The simple two-phase AC signal sources are easily produced by using flow rates than a corresponding single-phase structure. The simple two-phase AC signal sources are easily produced by using
inverter buffers, which is a considerable improvement compared to the multi-phase AC signals required by other electrokinetic inverter buffers, which is a considerable improvement compared to the multi-phase AC signals required by other electrokinetic
micropumping methods, such as traveling wave structures. micropumping methods, such as traveling wave structures.
KeywordsbioMEMS–Lab-on-a-chip–DEP–ACEO–ACET–Microfluidics–Micropumping–Asymmetric electrode arrays KeywordsbioMEMS–Lab-on-a-chip–DEP–ACEO–ACET–Microfluidics–Micropumping–Asymmetric electrode arrays
Microfluidics and Nanofluidics 01/2011; 10(3):521-529. · 2.67 Impact Factor
[Show abstract][Hide abstract] ABSTRACT: The ever increasing demand for low power DSP applications has directed researchers to contemplate a variety of potential approaches in different contexts. In this regard, using some alternative number systems, which inherently are capable of reducing the hardware complexity, have been propounded. In this work, a 2DLNS-based platform for multiplication intensive DSP applications is presented. Implementing an FIR filter structure on this basis shows outstanding privilege to its binary counterpart in terms of VLSI area and power consumption. I. INTRODUCTION Since most of Digital Signal Processing (DSP) algorithms are reliant heavily on multiplication, pursuing more efficient multiplication schemes have always been an active area of research in the field of computer arithmetic. In this regard, some attentions have been recently directed to making use of other number systems rather than traditional binary num- ber system. In Logarithmic Number System (LNS), every multiplication is replaced with an addition, therefore LNS has been propounded as an appropriate alternative number system in literature (1). The Multi-Dimensional Logarithmic Number System (MDLNS) can be considered as an multiple- base extension to LNS with an added advantage of having the capability to gain from the use of multiple digits. Whilst in MDLNS the reduced hardware complexity leads to power consumption savings, a larger dynamic range and more precise mapping of binary data are also achieved. In MDLNS, the mathematical operations over different bases and digits are completely independent which provides more potential for parallelism and may lead to more speed (2). A Finite Im- pulse Response (FIR) filter implementation requires a digital processor to perform multiplication over sequences of sampled values of input data and filter coefficients. Therefore, it may be considered as an appropriate context to examine the efficiency of MDLNS in a DSP application. This paper presents a typical FIR filter implementation in a 2DLNS-based platform. The rest of the paper is organized as follows. Section 2 introduces MDLNS and its properties. In section 3, the concept and algorithm of an FIR filter design are briefly reviewed. Section 4 includes a typical FIR filter implementation in two binary- based and 2DLNS-based structures and finally the synthesis results will be compared and the discussion will be concluded in section 5.
[Show abstract][Hide abstract] ABSTRACT: In new DSP applications, reconfigurable architectures have emerged to provide a flexible, high-performance, high-speed and low-power implementation platform for wireless embedded devices. Since some DSP algorithms rely heavily on multiplication, there are still demands for more efficient multiplication structures. In this study, two reconfigurable recursive multipliers are presented. The authors' architectures combine some of the flexibility of software with the high performance of hardware through implementing different levels of recursive multiplication schemes on a two-dimensional logarithmic number system (2DLNS) processing structure. The data are split into a number of smaller sections, where each section is converted to a 2-digit 2DLNS (2 bases) representation. The dynamic range reduction and logarithmic characteristics of computing with two orthogonal base exponents in this number system allows multiplication to be implemented with simple parallel small adders. The authors' architectures are able to perform single and double precision multiplications, as well as fault tolerant and dual throughput single precision operations. The implementations demonstrate the efficiency of 2DLNS in multiplication intensive DSP applications and show outstanding results in terms of operation delay and dynamic power consumption.
IET Circuits Devices & Systems 10/2010; · 0.91 Impact Factor
[Show abstract][Hide abstract] ABSTRACT: In the area of signal processing, digital circuits are advantageous in terms of lower sensitivity to noise and process variations, simplicity of design, programmability and test, while they attain higher speed, more functionality per chip, lower power dissipation or lower cost. Since some of DSP algorithms heavily rely on multiplication, there are constant demands for more efficient multiplication structures. In this paper, 2DLNS-based multiplication architectures with two different levels of recursion are presented. Our architectures combine some of the flexibility of software with the high performance of hardware through implementing the recursive multiplication schemes on a 2DLNS processing structure. The implementations demonstrate the efficiency of 2DLNS in DSP applications and show outstanding results in terms of operation delay and dynamic power consumption.
Circuits and Systems (ISCAS), Proceedings of 2010 IEEE International Symposium on; 07/2010
[Show abstract][Hide abstract] ABSTRACT: This paper presents interpolation-free fractional-pixel motion estimation (FME) algorithms and efficient hardware prototype
of one of the proposed FME algorithms. The proposed algorithms use a mathematical model to approximate the matching error
at fractional-pixel locations instead of using the block matching algorithm to evaluate the actual matching error. Hence,
no interpolation is required at fractional-pixel locations. The matching error values at integer-pixel locations are used
to evaluate the mathematical model coefficients. The performance of the proposed algorithms has been compared with several
FME algorithms including the full quarter-pixel search (FQPS) algorithm, which is used as part of the H.264 reference software.
The computational cost and the performance analysis show that the proposed algorithms have about 90% less computational complexity
than the FQPS algorithm with comparable reconstruction video quality (i.e., approximately 0.2 dB lower reconstruction PSNR
values). In addition, a hardware prototype of one of the proposed algorithms is presented. The proposed architecture has been
prototyped using the TSMC 0.18 μm CMOS technology. It has maximum clock frequency of 312.5 MHz, at which, the proposed architecture
can process more than 70 HDTV 1080p fps. The architecture has only 13,650 gates. The proposed architecture shows superior
performance when compared with several FME architectures.
Journal of Signal Processing Systems 05/2010; · 0.56 Impact Factor
[Show abstract][Hide abstract] ABSTRACT: This paper presents the Video-Active RAM (VA-RAM) architecture for video coding applications. VA-RAM is a processor-in-memory architecture customized for video coding applications. The VA-RAM architecture has been used to implement several video coding algorithms. A prototype of the VA-RAM for block-based integer-pixel ME has been fabricated using the TSMC 0.18 um CMOS technology. The architecture uses 89,687 gates and 18,976 bits of on-chip memory. At a maximum clock frequency of 125 MHz, the fabricated chip is able to process 15 4CIF fps. It consumes 84.68 mW at 125 MHz and has core area of 2.9 mm2.
International Symposium on Circuits and Systems (ISCAS 2010), May 30 - June 2, 2010, Paris, France; 01/2010
[Show abstract][Hide abstract] ABSTRACT: This paper presents low-complexity algorithm for fractional-pixel motion estimation (FME). The proposed algorithm uses a mathematical model to approximate the matching error at fractional-pixel locations. Hence, no interpolation is required at fractional-pixel locations. The matching error values at integer-pixel locations are used to evaluate the model coefficients. The performance of the proposed algorithm has been compared with other FME algorithms including the full quarter-pixel search (FQPS) algorithm. The performance analysis shows that the proposed algorithm has about 93% less computational complexity than the FQPS algorithm for approximately 0.2 dB drop in the reconstruction PSNR values.
Image Processing (ICIP), 2009 16th IEEE International Conference on; 12/2009
[Show abstract][Hide abstract] ABSTRACT: In this paper, we apply mixture theory to quantitatively predict the transient behavior of drug delivery by using a microneedle array inserted into tissue. In the framework of mixture theory, biological tissue is treated as a multi-phase fluid saturated porous medium, where the mathematical behavior of the tissue is characterized by the conservation equations of multi-phase models. Drug delivery by microneedle array imposes additional requirements on the simulation procedures, including drug absorption by the blood capillaries and tissue cells, as well as a moving interface along its flowing pathway. The contribution of this paper is to combine mixture theory with the moving mesh methods in modeling the transient behavior of drug delivery into tissue. Numerical simulations are provided to obtain drug concentration distributions into tissues and capillaries.
Biomechanics and Modeling in Mechanobiology 08/2009; 9(1):77-86. · 3.33 Impact Factor
[Show abstract][Hide abstract] ABSTRACT: We present a new circuit topology for potentiostats that interface with three-electrode amperometric electrochemical sensors. In this new topology, a current-copying circuit, e.g., a current mirror, is placed in the sensor current path to generate a mirrored image of the sensor current. The mirrored image is then measured and processed instead of the sensor current itself. The new potentiostat topology consumes very low power, occupies a very small die area, and has potentially very low noise. These characteristics make the new topology very suitable for portable or bioimplantable applications. In order to demonstrate the feasibility of the new topology, we present the results of a potentiostat circuit implemented in a 0.18-mum CMOS process. The circuit converts the sensor current to a frequency-modulated pulse waveform, for which the time difference between two consecutive pulses is inversely proportional to the sensor current. The potentiostat measures the sensor current from 1 nA to 1 muA with better than 0.1% of accuracy. It consumes only 70 muW of power from a 1.8-V supply voltage and occupies an area of 0.02 mm<sup>2</sup>.
Circuits and Systems I: Regular Papers, IEEE Transactions on 08/2009; · 2.30 Impact Factor
[Show abstract][Hide abstract] ABSTRACT: Fabrication results for MEMS-based microneedle arrays are presented in this paper. The microneedle array was fabricated by employing a bi-mask technique to facilitate sharp tips, a cylindrical body and side openings. The presented array has advantages over previously published microneedle arrays in terms of ease of fabrication and bonding; high needle density and robustness; and side openings, which are expected to minimize the potential for clogging from skin debris during insertion. In addition, control over the process via etch-stop markers employed as stop layers, which assure the depth of long blind holes and the structure of the needle top, allows for different needle lengths and needle top structures to be easily implemented. The preliminary fluid flow and insertion experiments were performed to demonstrate the efficiency of the microneedle arrays.
[Show abstract][Hide abstract] ABSTRACT: A remotely powered implantable microsystem for continuous blood glucose monitoring is presented. The microsystem consists of a microfabricated glucose biosensor flip-chip bonded to a transponder chip. The transponder chip is inductively powered by an external reader with a 13.56-MHz carrier. It then measures the output signal of the glucose biosensor and transmits the measured data back to the external reader using load-shift keying (LSK). The microsystem has a volume of 32 mm<sup>3</sup>. The procedures for the microfabrication of the glucose sensor and the assembly of the microsystem are described along with the description of the circuit blocks of the transponder chip. The transponder chip has been fabricated with the TSMC 0.18-mum CMOS process and has a total area of 1.3 x 1.3 mm<sup>2</sup>. The chip can measure the sensor output current ranging from 1 nA to 1 muA with less than 0.3% nonlinearity error, provided that the amplitude of the received RF signal is higher than 2.6 V; the circuit consumes a total current of about 110 muA.
IEEE Transactions on Biomedical Circuits and Systems 07/2009; · 3.15 Impact Factor
[Show abstract][Hide abstract] ABSTRACT: Motion Estimation/Compensation is one of the most critical modules in a typical digital video encoder. Many implementation tradeoffs should be considered while designing such a module. This paper focuses on the implementation of several motion estimation algorithms and investigates the differences between them according to different evaluation metrics. The algorithms are evaluated with respect to different parameters and are applied on different video sequences with different resolutions and types of motion.
CSIE 2009, 2009 WRI World Congress on Computer Science and Information Engineering, March 31 - April 2, 2009, Los Angeles, California, USA, 7 Volumes; 01/2009