[Show abstract][Hide abstract] ABSTRACT: A compact wireless clock distribution system with an external planar array antenna which can provide phase and amplitude distributions suitable for synchronizing circuits over a 35-mm diameter circular area at 3 GHz is proposed. The computer systems using this wireless clock distribution can have a comparable form factor as systems using a conventional clock network. The system is composed of a transmitter with an off-chip antenna, and multiple clock receivers with on-chip antennas distributed over an integrated circuit or over multiple ICs. The transmitter, which was fabricated in a 130-nm CMOS process, generates a 17-GHz clock signal which is periodically amplitude-modulated in order to initialize all of the receivers' clock dividers to the same clock phase. Besides increasing the synchronization area, this wireless approach effectively eliminates the dispersion problem in conventional clock networks. The experimental results presented show the feasibility and potential benefits of the wireless clock distribution system using an external antenna.
[Show abstract][Hide abstract] ABSTRACT: A receiver for wireless clock distribution runs at 2.25GHz with 5pspp jitter. The clock is distributed as a sine wave at 8 times the actual clock frequency to mitigate dispersion. The receiver includes an initialization circuit and a frequency divider with 16 quantized programmable delays for skew reduction
[Show abstract][Hide abstract] ABSTRACT: A compact wireless clock distribution system with an external planar array antenna which can provide phase uniformity suitable for synchronizing at 3 GHz over an area 4-5 × larger than that previously thought possible is proposed. The system is composed of an off-chip antenna and multiple clock receivers distributed over an integrated circuit or over multiple IC's. The system has a comparable form factor as a system using conventional clock system. A technique to synchronize the receivers is proposed. The transmitter and receiver circuits required for the system have been fabricated in a 130-nm CMOS process. Using a transmitter, an amplitude modulated 17-GHz clock signal is generated and transmitted. The signal is picked up by a receiver and utilized to initialize/synchronize the receiver and to generate a local clock signal in the presence of a heatsink.
Custom Integrated Circuits Conference, 2005. Proceedings of the IEEE 2005; 10/2005
[Show abstract][Hide abstract] ABSTRACT: The feasibility of integrating antennas and required circuits to form wireless interconnects in foundry digital CMOS technologies has been demonstrated. The key challenges including the effects of metal structures associated with integrated circuits, heat removal, packaging, and interaction between transmitted and received signals, and nearby circuits appear to be manageable. This technology can potentially be applied for implementation of a true single-chip radio for general purpose communication, on-chip and inter-chip data communication systems, RFID tags, RF sensors/radars, and others.
IEEE Transactions on Electron Devices 08/2005; 52(7-52):1312 - 1323. DOI:10.1109/TED.2005.850668 · 2.47 Impact Factor
[Show abstract][Hide abstract] ABSTRACT: A 14-GHz 256/257 dual-modulus prescaler is implemented using secondary feedback in the synchronous 4/5 divider on a 0.18-μm foundry CMOS process. The dual-modulus scheme utilizes a 4/5 synchronous counter which adopts a traditional MOS current mode logic clocked D flip-flop. The secondary feedback paths limit signal swing to achieve high-speed operation. The maximum operating frequency of the prescaler is 14 GHz at V<sub>DD</sub>=1.8 V. Utilizing the prescaler, a 10.4-GHz monolithic phase-locked loop (PLL) is demonstrated. The voltage-controlled oscillator (VCO) operates between 9.7-10.4 GHz. The tuning range of the VCO is 690 MHz. The phase noise of the PLL and VCO at a 3-MHz offset with I<sub>vco</sub>=4.9 mA is -117 and -119 dBc/Hz, respectively. At the current consumption of I<sub>vco</sub>=8.1 mA, the phase noise is -122 and -122 dBc/Hz, respectively. The PLL output phase noise at a 50-kHz offset is -80 dBc/Hz. The PLL consumes ∼31 mA at V<sub>DD</sub>=1.8 V.
IEEE Transactions on Microwave Theory and Techniques 03/2004; 52(2-52):461 - 468. DOI:10.1109/TMTT.2003.821918 · 2.24 Impact Factor
[Show abstract][Hide abstract] ABSTRACT: A 10.4-GHz PLL with a 256/257 dual modulus prescaler implemented in a 0.18-μm CMOS process is presented. The prescaler with a 4/5 synchronous counter operates up to 14 GHz. The counter achieves this by using feedback. The phase noise levels of the PLL and VCO at a 3-MHz offset with I<sub>VCO</sub>=8.1 mA are -122 dBc/Hz. The PLL operates between 9.7 10.4 GHz, while drawing 34 mA at V<sub>DD</sub>=1.8 V.
VLSI Circuits Digest of Technical Papers, 2002. Symposium on; 02/2002
[Show abstract][Hide abstract] ABSTRACT: Low frequency noise of NMOS and PMOS transistors in a 0.25 μm
foundry CMOS process with a pure SiO<sub>2</sub> gate oxide layer is
characterized for the entire range of MOSFET operation. Surprisingly,
the measurement results showed that surface channel PMOS transistors
have about an order of magnitude lower 1/f noise than NMOS transistors
especially at V<sub>GS</sub>-V<sub>TH</sub> less than ~0.4 V The data
were used to show that a VCO using all surface channel PMOS transistors
can have ~14 dB lower close-in phase noise compared to that for a VCO
using all surface channel NMOS transistors
Radio Frequency Integrated Circuits (RFIC) Symposium, 2002 IEEE; 02/2002