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ABSTRACT: A low-phase-noise 0.35-mum CMOS push-push oscillator utilizing micromachined inductors is presented in this paper. With the micromachined high-Q inductors, the oscillator achieves an oscillating frequency of 30.9 GHz while exhibiting an output power of -4 dBm with a low phase noise of -102.3 dBc/Hz at 1-MHz offset and the figure of merit (FoM) of -171.4 dBc/Hz. The fundamental rejection is 30 dB. This oscillator achieves low phase noise, good FOM, high output power, and also demonstrates the highest operating frequency among previously published Si-based and GaAs-based VCOs using micromachined structures
Microwave Symposium Digest, 2006. IEEE MTT-S International; 07/2006
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ABSTRACT: This paper presents a compact 35-65 GHz Gilbert cell up-convert mixer implemented in TSMC 0.18-mum SiGe BiCMOS technology. Integrated broadband transformers and meandered thin-film microstrip lines were utilized to achieve a miniature chip area of 0.6 mm times 0.45 mm. The compact MMIC has a flat measured conversion loss of 7 plusmn 1.5 dB and LO suppression of more than 40 dB at the RF port from 35 to 65 GHz. The power consumption is 14 mW from a 4-V supply. This is a fully integrated millimeter-wave active mixer that has the smallest chip area ever reported, and also the highest operation frequency among up-conversion mixers using silicon-based technology
Radio Frequency Integrated Circuits (RFIC) Symposium, 2006 IEEE; 07/2006
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ABSTRACT: A downconversion double-balanced oscillator mixer using 0.18-mum CMOS technology is proposed in this paper. This oscillator mixer consists of an individual mixer stacked on a voltage-controlled oscillator (VCO). The stacked structure allows entire mixer current to be reused by the VCO cross-coupled pair to reduce the total current consumption of the individual VCO and mixer. Using individual supply voltages and eliminating the tail current source, the stacked topology requires 1.0-V low supply voltage. The oscillator mixer achieves a voltage conversion gain of 10.9 dB at 4.2-GHz RF frequency. The oscillator mixer exhibits a tuning range of 11.5% and a single-sideband noise figure of 14.5 dB. The dc power consumption is 0.2 mW for the mixer and 2.94 mW for the VCO. This oscillator mixer requires a lower supply voltage and achieves a higher operating frequency among recently reported Si-based self-oscillating mixers and mixer oscillators. The mixer in this oscillator mixer also achieves a low power consumption compared with recently reported low-power mixers
IEEE Transactions on Microwave Theory and Techniques 02/2006; · 1.85 Impact Factor
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ABSTRACT: A low insertion-loss single-pole double-throw switch in a standard 0.18-μm complementary metal-oxide semiconductor (CMOS) process was developed for 2.4- and 5.8-GHz wireless local area network applications. In order to increase the P<sub>1dB</sub>, the body-floating circuit topology is implemented. A nonlinear CMOS model to predict the switch power performance is also developed. The series-shunt switch achieves a measured P<sub>1dB</sub> of 21.3 dBm, an insertion loss of 0.7 dB, and an isolation of 35 dB at 2.4 GHz, while at 5.8 GHz, the switch attains a measured P<sub>1dB</sub> of 20 dBm, an insertion loss of 1.1 dB, and an isolation of 27 dB. The effective chip size is only 0.03 mm<sup>2</sup>. The measured data agree with the simulation results well, including the power-handling capability. To our knowledge, this study presents low insertion loss, high isolation, and good power performance with the smallest chip size among the previously reported 2.4- and 5.8-GHz CMOS switches.
IEEE Transactions on Microwave Theory and Techniques 02/2006; · 1.85 Impact Factor
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ABSTRACT: This letter presents a low phase noise 0.35-μm CMOS push-push oscillator utilizing micromachined inductors. This oscillator results in an improvement in phase noise compared with the previously published Si-based voltage-controlled oscillators (VCOs) around 20GHz. With the high-Q inductors introduced by the micromachined structure, the oscillator achieves an oscillating frequency of 22.2GHz while exhibiting an output power of -7.5dBm with a phase noise of -110.1dBc/Hz at 1-MHz offset. This work also demonstrates the highest operating frequency among previously published Si-based VCOs using micromachined structures.
IEEE Microwave and Wireless Components Letters 01/2006; · 1.72 Impact Factor
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ABSTRACT: A 24-GHz low-noise amplifier (LNA) was designed and fabricated in a standard 0.18-μm CMOS technology. The LNA chip achieves a peak gain of 13.1 dB at 24 GHz and a minimum noise figure of 3.9 dB at 24.3 GHz. The supply voltage and supply current are 1 V and 14 mA, respectively. To the author's knowledge, this LNA demonstrates the lowest noise figure among the reported LNAs in standard CMOS processes above 20 GHz.
IEEE Microwave and Wireless Components Letters 08/2005; · 1.72 Impact Factor
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ABSTRACT: A 131 GHz cross-coupled push-push voltage controlled oscillator (VCO) is realized in 90-nm CMOS technology. It can be tuned from 129.8 to 132 GHz, with an estimated phase noise of -108.4 dBc/Hz at 10 MHz offset. The oscillator provides a push-push output power of -15.2 dBm and a fundamental output power of +0.33 dBm, under core current of 20 mA from a 1-V supply voltage. Maximum push-push and fundamental output powers are -11.4 dBm and +2.1 dBm, respectively. To the authors' knowledge, this is the highest frequency CMOS VCO ever reported.
Radio Frequency integrated Circuits (RFIC) Symposium, 2005. Digest of Papers. 2005 IEEE; 07/2005
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ABSTRACT: A low insertion loss SPDT switch in a standard 0.18-μm CMOS process was developed for 2.4- and 5.8-GHz WLAN applications. In order to reduce the insertion loss and increase the P<sub>1dB</sub>, the floating-body circuit topology is proposed. The series-shunt switch achieves a measured P<sub>1dB</sub> of 20 dBm, an insertion loss of 1.1 dB, and an isolation of 27 dB at 5.8 GHz. It also achieves a measured insertion loss of 0.65 dB and an isolation of 35 dB at 2.4 GHz. The effective chip size is only 0.03 mm<sup>2</sup>. The measured data agree well with the simulation results. This work presents low insertion loss, high isolation and good power performance with the smallest chip size compared to previously reported 2.4- and 5.8-GHz CMOS switches.
Radio Frequency integrated Circuits (RFIC) Symposium, 2005. Digest of Papers. 2005 IEEE; 07/2005
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04/2005; , ISBN: 9780471654506
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ABSTRACT: A 6-stage travelling wave amplifier (TWA) implemented in a bulk 90nm CMOS technology is presented. By utilizing gate-line capacitive division and low-loss coplanar waveguides, the fabricated TWA exhibits 7.4dB gain with a 3dB bandwidth of 80GHz while maintaining input and output return losses better than 8dB from dc to 100GHz. A GBW of 190GHz is achieved.
Solid-State Circuits Conference, 2005. Digest of Technical Papers. ISSCC. 2005 IEEE International; 03/2005
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ABSTRACT: The designs of two fully integrated CMOS cascode distributed amplifiers (DAs) with 14-GHz and 22-GHz bandwidth are presented. Cascode gain cells and m-derived matching sections are used to enhance the gain and bandwidth performance. These amplifiers demonstrated the highest frequency and widest bandwidth of operation for amplifiers using regular CMOS processes to date. This paper also describes the analysis to design the cascode CMOS DA, together with the small-signal models, EM simulation of the spiral inductors on the silicon substrate, and the analysis of the cascode device. Good agreement between measured and simulated results was achieved for both of the DA designs.
IEEE Journal of Solid-State Circuits 09/2004; · 3.23 Impact Factor
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ABSTRACT: Two broadband transimpedance amplifiers (TIAs) for optical applications were realized in a 0.18-μm CMOS technology. The first TIA, cascading two three-stage cascode distributed amplifiers, achieves a transimpedance gain of 58 bBΩ and a bandwidth of 15 GHz. The other, using a cascode distributed amplifier, achieves a transimpedance gain of 48 dBΩ and a bandwidth of 30 GHz. The TIAs utilize a distributed technique with cascode gain cells to enhance the gain and bandwidth performance. This technique provides TIAs with ultra-broad bandwidth.
Radio Frequency Integrated Circuits (RFIC) Symposium, 2004. Digest of Papers. 2004 IEEE; 07/2004
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ABSTRACT: The boundary-scan test provides a structural test solution for the densely packed digital electronics. For RF devices, the structural test also provides a good diagnostic resolution to the structural defects of RF circuits, especially for the high pin-count RF-SOCs. In this paper, the boundary-scan test is implemented on a 5-GHz RF pin using LC isolation networks to connect the RF lines and the boundary-scan cell, which isolates the RF circuitry from the digital boundary scan cell. This technique overcomes the parasitic loading problems and provides a minimum RF performance degradation to a RFIC. The measurement results show only 0.4-dB gain degradation in a 5-GHz amplifier with a boundary-scan cell and LC isolation networks.
VLSI Test Symposium, 2004. Proceedings. 22nd IEEE; 05/2004
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ABSTRACT: A 63 GHz VCO using a 0.25 μm 1P6M CMOS is presented. It achieves an output power of -4 dBm without any output amplifier. This VCO is tunable over a 2.5 GHz range and its phase noise is -85 dBc/Hz at 1 MHz offset. The IC covers an area of 0.315 mm<sup>2</sup> and consumes 118 mW maximum.
Solid-State Circuits Conference, 2004. Digest of Technical Papers. ISSCC. 2004 IEEE International; 03/2004
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ABSTRACT: A 4.5-6 GHz CMOS low-voltage wideband variable gain low noise amplifier (VGLNA) with wide gain-control range has been demonstrated in this paper. The VGLNA, operating at a supply voltage as low as 1 V, achieves a small signal gain of 20 dB and 3-dB bandwidth of 1.5 GHz with good return losses. The noise figure is 3.5 dB at 5.5 GHz. A figure-of-merit for gain efficiency (Gain/PDC) of 1.23 dB/mW is achieved, which is believed to be the best among reported results for a CMOS VGLNA operating at multi-GHz frequency.
Microwave Conference, 2003. 33rd European; 11/2003
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ABSTRACT: A 0.5-14-GHz distributed amplifier (DA) using 0.18-μm CMOS technology has been presented. It demonstrates the highest gain bandwidth product reported for a CMOS amplifier using a standard Si-based IC process. This DA chip achieves measured results of 10.6±0.9 dB gain, NF between 3.4 and 5.4 dB with good return losses better than from 0.5 to 14 GHz. The measured output IP3 and P<sub>ldB</sub> are +20 dBm and +10 dBm, respectively, from 2 to 10 GHz.
VLSI Circuits, 2003. Digest of Technical Papers. 2003 Symposium on; 07/2003
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ABSTRACT: A CMOS distributed amplifier (DA) covering 0.6 to 22 GHz is presented in this paper. Cascode gain cells and m-derived matching sections are used to enhance the gain and bandwidth performance. The DA chip achieves measured gain of 7.3 ± 0.8 dB with chip area of 0.9 × 1.5 mm<sup>2</sup> including testing pads. The amplifier was fabricated in a standard 0.18-μm CMOS technology and demonstrated the highest frequency and bandwidth of operation among previously reported amplifiers using regular CMOS processes to date.
Radio Frequency Integrated Circuits (RFIC) Symposium, 2003 IEEE; 07/2003
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ABSTRACT: A 5.8-GHz two-stage high-linearity low-voltage CMOS low-nose
amplifier (LNA) has been developed in a 0.35-μm pure digital CMOS
technology without any additional mask or post-processing steps. A
two-stage architecture is used to simultaneously optimize the gain and
noise performance. Based on the modified CMOS model valid for RF range,
the LNA with fully on-chip input, output and inter-stage matching was
designed to verify the two-stage LNA architecture. This LNA chip
achieves measured results of 3.2-dB NF, +6.7-dBm IIP3 and -3.7-dBm
output P<sub>1dB</sub> at 5.8 GHz. A figure-of-merit for linearity
(output IP3/P<sub>DC</sub>) of 1.2 is achieved, which is believed to be
among the best reported for a CMOS low-noise amplifier operating at 5-6
GHz ISM band. The effective circuit area is only 0.63 × 0.46 mm
<sup>2</sup>
Radio Frequency Integrated Circuits (RFIC) Symposium, 2002 IEEE; 02/2002
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ABSTRACT: A 4.5-6 GHz CMOS low-voltage wideband variable gain low noise amplifier (VGLNA)with wide gain-control range has been demonstrated in this paper. The VGLNA,operating at a supply voltage as low as 1 V, achieves a small signal gain of 20 dB and 3-dB bandwidth of 1.5 GHz with good return losses.The noise figure is 3.5 dB at 5.5 GHz.A figure-of-merit for gain efficiency (Gain/PDC)of 1.23 dB/mW is achieved,which is believed to be the best among reported results for a CMOS VGLNA operating at multi-GHz frequency.
