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ABSTRACT: In this paper the authors examined and compared the relative contribution between a switching pattern and process parameter variation on bus performance. The authors concentrated on interconnect parameter variation in global bus interconnects. The variation of the parameter values between individual interconnects occurs when process technologies head towards nano-scale. In addition to this "passive" process-dependent parameter variation active variation in interconnect performance due to switching data patterns in adjacent wires of a bus structure were examined. A noise voltage in a quiet wire and the propagation delay of a signal are performance metrics in the comparisons. The effect of signal rise time is also considered. The comparisons were made using International Technology Roadmaps for Semiconductors (ITRS) from a 180-nm half-pitch node to a 22-nm node.
Signals, Circuits and Systems, 2005. ISSCS 2005. International Symposium on; 08/2005
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ABSTRACT: It is envisioned that future system-on-chip hardware platform designs will be based on reuse of a customizable processor core. Consequently, being able to quickly evaluate the key performance metrics associated with specific points in the design space becomes essential. Development of an early design phase performance estimation method for logic blocks of an extensible processor core is described. The processor blocks were systematically synthesized with varying constraints for reference and the corresponding Rent's exponents were extracted from the results. The impact of synthesis-originated design space discontinuities on the accuracy of physical performance estimation was evaluated by applying linear regression on the resulting design points.
VLSI, 2003. Proceedings. IEEE Computer Society Annual Symposium on; 03/2003
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ABSTRACT: In this paper we propose an interconnection scheme for the autonomous error-tolerant (AET) cell introduced in a paper by Valtonen et al. (2001). The objective here is to partition the system into identical, physically autonomous and highly configurable cells that can operate without outside control or synchronization. In billion transistor Network-on-Chip (NoC) circuits, an AET cell fabric could prove highly flexible and reliable, and allow for low replication costs, due to homogeneousity. However, many challenges persist before a useful system can be constructed: the need for (i) scalable long-distance communication-global bus wiring fits poorly into a homogeneous, symmetric fabric and limits scalability, (ii) flexible communication-cells in all directions, within a given range, should be accessible and (iii) self-synchronizing topologies, due to the absence of external synchronization; (iv) the interconnect scheme is to be implemented using near-future technology generations, and (v) the fabric should be efficient when constituting billions of cells.
Circuits and Systems, 2002. ISCAS 2002. IEEE International Symposium on; 02/2002
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ABSTRACT: We present a case study in finding optimized processor architectures for a given protocol processing application. The process involves application analysis, hardware/software partitioning and optimization, and evaluation of design quality through simulations, estimations and synthesis. The case study was targeted at processing key IPv6 routing functions at 200 MHz using 0.18 μm CMOS technology. A comparison to an implementation on a commercial processor revealed that the captured architectures provided similar or better performance. Especially checksum calculation was efficient in the captured architectures.
Digital System Design, 2005. Proceedings. 8th Euromicro Conference on;
