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A.M.A. Ali,
A. Morgan,
C. Dillon,
G. Patterson,
S. Puckett,
P. Bhoraskar,
H. Dinc, M. Hensley,
R. Stop,
S. Bardsley,
D. Lattimore,
J. Bray,
C. Speir,
R. Sneed
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ABSTRACT: This paper describes a 16-bit 250 MS/s ADC fabricated on a 0.18 BiCMOS process. The ADC has an integrated input buffer with a new linearization technique that improves its distortion by 5-10 dB and lowers its power consumption by 70% relative to the state of the art. It demonstrates a new background calibration technique to correct the residue amplifier (RA) gain errors and lower its power consumption. This summing node sampling (SNS) calibration technique is based on sampling the summing-node voltage of the residue amplifier and using it with the corresponding residue to estimate the amplifier open loop gain. The ADC achieves an SNDR of 76.5 dB and consumes 850 mW from a 1.8 V supply, while the input buffer consumes 150 mW from a 3 V supply. Up to 125 MS/s, the SFDR is greater than 100 dB for input frequencies up to 100 MHz and 90 dB up to 300 MHz input frequency. At 250 MS/s, the SFDR is greater than 95 dB up to 100MHz and 85 dB up to 300 MHz.
IEEE Journal of Solid-State Circuits 01/2011; · 3.23 Impact Factor
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M. Hensley,
C. Speir,
R. Stop,
K. Behel,
C. Moreland,
G. Patterson,
D. Kelly,
M. Manglani,
M. Elliott,
S. Puckett,
J. Young,
F. Murden
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ABSTRACT: An integrated circuit is presented which receives an input IF frequency in the range of 70-300 MHz, and achieves 117 dB of dynamic range in a 200 kHz bandwidth (BW). An automatic-gain-control (AGC) loop is placed around the analog-to-digital converter (ADC). Amplitude-modulation (AM) caused by gain switching is corrected digitally.
Custom Integrated Circuits Conference, 2004. Proceedings of the IEEE 2004; 11/2004
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ABSTRACT: An integrated low-noise amplifier, mixer, bandpass ΔΣ analog-to-digital converter (ADC), decimation filter, and two synthesizers implement a general-purpose back-end for a narrow-band superheterodyne receiver. The ΔΣ ADC is merged with the mixer and combines LC, active-RC, and switched-capacitor resonators to achieve low noise and robust operation with low power consumption. A variable full-scale feature adds an automatic-gain-control capability to the ADC while saving power and minimizing noise at low signal levels.
IEEE Journal of Solid-State Circuits 01/2003; · 3.23 Impact Factor
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Solid-State Circuits Conference, 2002. Digest of Technical Papers. ISSCC. 2002 IEEE International; 02/2002
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[show abstract]
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ABSTRACT: Summary form only given. A mixer plus multi-bit bandpass
ΣΔ ADC achieves 89 dB and 77 dB SNR in 35 kHz and 333 kHz
bandwidths at 273 MHz IF while consuming 16 mA from a 3 V supply. The 6
<sup>th</sup>-order ADC combines continuous-time LC and active RC
resonators with a discrete-time switched-capacitor resonator, and
includes an AGC capability. The IC is fabricated in a 0.35 μm BiCMOS
process
Solid-State Circuits Conference, 2002. Digest of Technical Papers. ISSCC. 2002 IEEE International; 02/2002
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ABSTRACT: This paper describes a 14-b analog-to-digital converter designed
in a complementary bipolar process. Although it uses a fairly
traditional three-stage subranging architecture, several nontraditional
techniques are incorporated to achieve 14 bits of performance at a clock
rate of 100 MHz. For linearity, the most critical of these is wafer
level trimming of the first subrange digital-to-analog converter.
Prototype silicon exhibits a spurious-free dynamic range of 90 dB
through the Nyquist frequency and a signal-to noise ratio of 74 dB while
dissipating 1.25 W
IEEE Journal of Solid-State Circuits 01/2001; · 3.23 Impact Factor
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ABSTRACT: A 14b three-stage ADC uses a complementary bipolar process to
achieve a 100MSample/s encode rate with a SFDR of >90 dB and an SNR
of 75 dB. While the design is based on a traditional multi-stage
architecture, the three encoder stages use serial-ripple converters.
Unlike the typical N-bit flash converter which requires 2-<sup>N-1</sup>
comparators, the serial-ripple converter has only N comparators. The
result is a smaller die area and lower power dissipation than flash.
This design uses a total of 16 comparators, and at the full sample rate
consumes 1250 mW. It is fabricated in a 0.8 μm double-poly
complementary bipolar process
Solid-State Circuits Conference, 2000. Digest of Technical Papers. ISSCC. 2000 IEEE International; 02/2000
