R. Blumgold

Wright State University, Dayton, OH, United States

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Publications (4)2.75 Total impact

  • S. Ren · R. Siferd · R. Blumgold · R. Ewing ·
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    ABSTRACT: A design procedure is presented for a hardware efficient FIR compensation filter as a component in a delta sigma modulator analog to digital converter using cascaded sine low pass filters. The combination of the sine low pass filters and the hardware efficient FIR compensation filter results in a 21% saving in hardware (chip area) compared to a single FIR low pass filter
    Circuits and Systems, 2005. 48th Midwest Symposium on; 09/2005
  • S. Ren · R. Siferd · R. Blumgold ·
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    ABSTRACT: Many system on chip (SOC) architectures are pushing the analog to digital interface into the RF/IF region. A critical component for such architectures is a band pass analog to digital converter (BPADC). A parallel time interleaved (PTI) delta sigma BPADC is presented which supports RF/IF center frequencies for SOC applications. Three low pass delta sigma modulators sampling at 1 GHz are time interleaved to obtain a BPADC with center frequencies of 1 or 2 GHz in 0.18μm CMOS technology. Resolution depends on bandwidth with 8 bits achievable for a 100 MHz bandwidth and 1 GHz sampling frequencies for the modulators. The BPADC center frequencies, resolution, and bandwidth can be modified by changing the sampling frequency of the modulators or the number of modulators that are time interleaved.
    SOC Conference, 2004. Proceedings. IEEE International; 10/2004
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    ABSTRACT: A T-gate structure has been implemented in the fabrication of fully depleted silicon-on-insulator MOSFETs. The T-gate process is fully compatible with the standard CMOS and the resulting reduction of gate-resistance significantly improved the RF performance. Measured f/sub max/ is 76 GHz and 63 GHz for n- and p-MOSFET with 0.2-/spl mu/m gate length, respectively. At 2 GHz, a minimum noise figure of 0.4 dB was measured on an n-MOSFET with the T-gate structure.
    IEEE Electron Device Letters 02/2002; 23(1-23):52 - 54. DOI:10.1109/55.974810 · 2.75 Impact Factor
  • Source
    C. Cerny · R. Blumgold · J. Cook · S. Bibyk · J. Fisher · R. Siferd · Si-Yu Ren ·
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    ABSTRACT: An important aspect in developing digital receivers is the reduction of analog components, which tend to be temperature sensitive and require calibration and result in a reduction in receiver accuracy. Digital receivers are a long-term goal of the Air Force, which strive for increased functionality interactive capability amongst air, space and ground based platforms. Therefore, in the proper designing of that digital receiver an intricate tradespace exists in order to maintain the power performance relationship needed to meet platform requirements, and reducing acquisition and lifecycle costs. This paper summarizes efforts to completely analyze two complementary enhancement-mode technologies, GaAs CHFET and SOI CMOS, which could be implemented at the front end of the digital receiver and result in an appropriate power/performance improvement. This effort begins with a detailed radio frequency (RF) characterization of each technology, the building of a complete RF model, and the correct choice of enhancement-mode, high performance mixed-signal circuit designs. This type of ground level approach is critical to any future digital receiver architecture where platform power budget constraints must be met, while producing the maximum performance
    National Aerospace and Electronics Conference, 2000. NAECON 2000. Proceedings of the IEEE 2000; 02/2000