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Publications (2)2.79 Total impact

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    ABSTRACT: A T-gate structure has been implemented in the fabrication of fully depleted silicon-on-insulator MOSFETs. The T-gate process is fully compatible with the standard CMOS and the resulting reduction of gate-resistance significantly improved the RF performance. Measured f/sub max/ is 76 GHz and 63 GHz for n- and p-MOSFET with 0.2-/spl mu/m gate length, respectively. At 2 GHz, a minimum noise figure of 0.4 dB was measured on an n-MOSFET with the T-gate structure.
    IEEE Electron Device Letters 02/2002; · 2.79 Impact Factor
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    ABSTRACT: An important aspect in developing digital receivers is the reduction of analog components, which tend to be temperature sensitive and require calibration and result in a reduction in receiver accuracy. Digital receivers are a long-term goal of the Air Force, which strive for increased functionality interactive capability amongst air, space and ground based platforms. Therefore, in the proper designing of that digital receiver an intricate tradespace exists in order to maintain the power performance relationship needed to meet platform requirements, and reducing acquisition and lifecycle costs. This paper summarizes efforts to completely analyze two complementary enhancement-mode technologies, GaAs CHFET and SOI CMOS, which could be implemented at the front end of the digital receiver and result in an appropriate power/performance improvement. This effort begins with a detailed radio frequency (RF) characterization of each technology, the building of a complete RF model, and the correct choice of enhancement-mode, high performance mixed-signal circuit designs. This type of ground level approach is critical to any future digital receiver architecture where platform power budget constraints must be met, while producing the maximum performance
    National Aerospace and Electronics Conference, 2000. NAECON 2000. Proceedings of the IEEE 2000; 02/2000