B. B. Triplett

Stanford University, Palo Alto, California, United States

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Publications (11)17.01 Total impact

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    ABSTRACT: This study reports on the first experimental observations of electrically biased paramagnetic defects at 800 ° C N <sub>2</sub> annealed Hf <sub>x</sub> Si <sub>1-x</sub> O <sub>2</sub> ( x=0.4 , and 0.6)/(100)Si and HfO <sub>2</sub>/(100) Si interfaces in metal oxide silicon structures. These defects are examined by electrical-field controlled electron spin resonance (ESR) and correlated with capacitance-voltage (C-V) analysis. Distributions of ESR measured density of interface traps (ESR- D<sub> it </sub> ), P<sub>b0</sub> and P<sub>b1</sub> , exhibit distinct charge humps and peaks in the Si bandgap with maximum defect density of 0.9–1.9×10<sup>12</sup> cm <sup>-2</sup>  eV <sup>-1</sup> in the Hf <sub>0.4</sub> Si <sub>0.6</sub> O <sub>2</sub>/ Si interface. Three P<sub>b0</sub> and one P<sub>b1</sub> charged ESR- D<sub> it </sub> peaks with density of 1.7–2.8×10<sup>12</sup> cm <sup>-2</sup>  eV <sup>-1</sup> are observed in the Hf <sub>0.6</sub> Si <sub>0.4</sub> O <sub>2</sub>/ Si interface. Cross-sectional transmission electron microscopic images show decreasing interfacial layer (IL) thickness with increasing hafnium composition (x) at the Hf <sub>x</sub> Si <sub>1-x</sub> O <sub>2</sub>/ Si interface. The roughest IL observed at the HfO <sub>2</sub>/ Si interface may have contributed to an ESR- D<sub> it </sub> of P<sub>b0</sub> greater than 2×10<sup>13</sup> cm <sup>-2</sup>  eV <sup>-1</sup> and a pinned Fermi level near the midgap. It appears that the energy distributions of interface defects in Hf <sub>x</sub> Si <sub>1-x</sub> O <sub>2</sub>/ Si and HfO <sub>2</sub>/ Si have different signatures compared to those at SiO <sub>2</sub>/ Si interface, especially the charged peak near the midgap.
    Journal of Applied Physics 08/2008; · 2.21 Impact Factor
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    ABSTRACT: Electron spin resonance measurements on 4 and 40 nm thick ( Hf O <sub>2</sub>)<sub>0.6</sub>( Si O <sub>2</sub>)<sub>0.4</sub> and ( Hf O <sub>2</sub>)<sub>0.4</sub>( Si O <sub>2</sub>)<sub>0.6</sub> high- κ films on (100)Si wafers detected P<sub>b0</sub> and P<sub>b1</sub> defects at the dielectric/Si interface and verified their identities with g value mapping. Annealings of a 4 nm thick ( Hf O <sub>2</sub>)<sub>0.6</sub>( Si O <sub>2</sub>)<sub>0.4</sub> film in nitrogen at 800 and 1000 ° C monotonically lowered total interface states. In contrast, the same annealings monotonically increased the total interface states observed in 40 nm thick films of both compositions. For the 4 nm technologically relevant thickness, the annealed ( Hf O <sub>2</sub>)<sub>0.6</sub>( Si O <sub>2</sub>)<sub>0.4</sub> composition on (100)Si had lower interface states than the ( Hf O <sub>2</sub>)<sub>0.4</sub>( Si O <sub>2</sub>)<sub>0.6</sub> composition on (100)Si. After nitrogen annealing at 800 ° C , a third defect believed to be the EX, appears in larger quantities in the thicker 40 nm films.
    Journal of Applied Physics 02/2007; · 2.21 Impact Factor
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    ABSTRACT: Growth of zirconia (ZrO 2)-based gate dielectrics on germanium Ge substrates by oxidation using activated oxygen species produced by ultraviolet radiation UV/ozone is reported here. In this technique, a thin layer of zirconium Zr metal 10–30 Å is deposited by physical vapor deposition on Ge and subsequently oxidized in reactive oxygen. X-ray photoelectron spectroscopy XPS analysis indicates complete oxidation of the Zr metal. High resolution transmission electron microscopy TEM of UV-ozone oxidized ZrO 2 on Ge indicates a sharp interface between the oxide and the substrate. However, conventional TEM is not well suited for identifying a Ge oxide layer in this system due to the closeness in atomic number of Zr and Ge. XPS spectra suggest the presence of a substoichiometric Ge oxide phase at the ZrO 2 /Ge interface. Depth profiling using angle-resolved XPS was performed on ZrO 2 /Ge gate stacks of varying oxide thickness. The results indicate that the amount of Ge oxide is dependent upon the ZrO 2 overlayer thickness, suggesting that the interfacial layer can be controlled by the oxidation conditions. © 2004 American Institute of Physics.
    Journal of Applied Physics 07/2004; · 2.21 Impact Factor
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    ABSTRACT: In this paper the two metal oxide dielectrics (ZrO2 and HfO2) deposited in the same chamber with the same technique using a newly developed self-aligned gate-last MOSFET process are compared. The compared results suggested that using either ZrO2 or HfO2 would provide similar on-to-off current ratio at a given device size.
    01/2003;
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    ABSTRACT: For the first time, we have successfully demonstrated the feasibility of integrating a high-permittivity (/spl kappa/) gate dielectric material zirconium oxide into the MOS capacitors fabricated on pure germanium substrates. The entire fabrication process was essentially performed at room temperature with the exception of a 410/spl deg/C forming gas anneal. After processing steps intended to remove the germanium native oxide interlayer between the zirconium oxide dielectric and germanium substrate, an excellent capacitance-based equivalent SiO/sub 2/ thickness (EOT) on the order of 5-8 /spl Aring/ and capacitance-voltage (C-V) characteristics with hysteresis of 16 mV have been achieved. Additionally, excellent device yield and uniformity were possible using this low thermal budget process.
    IEEE Electron Device Letters 09/2002; · 2.79 Impact Factor
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    ABSTRACT: Thermal stability of gate stack structures composed of ZrO <sub>2</sub> gate dielectrics and silicon electrodes was investigated. The ZrO <sub>2</sub> films were deposited by atomic layer deposition, while the polycrystalline silicon electrodes were deposited using different variants of chemical (CVD) and physical vapor deposition (PVD). Zirconium silicide formation was noted in all CVD-electroded samples after subsequent annealing treatments at temperatures above 750 °C, but not in the room temperature PVD-electroded samples, even after gate annealing at 1050 °C. The dependence of zirconium silicide formation on the Si deposition process was explained using thermodynamic arguments which explicitly include the effects of oxygen deficiency of the metal oxide films. © 2002 American Institute of Physics.
    Applied Physics Letters 09/2002; · 3.79 Impact Factor
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    ABSTRACT: For the first time, we have successfully demonstrated the use of a high-κ gate dielectric material, ZrO<sub>2</sub>, for CMOS applications on a pure germanium substrate. Using a low-temperature formation technique, we achieved excellent C-V characteristics with hysteresis of 1.5 mV and a capacitance-based equivalent SiO<sub>2</sub> thickness (t<sub>ox,eq</sub>) of about 5 Å. Additionally, excellent device uniformity and very high device yield were attained.
    Device Research Conference, 2002. 60th DRC. Conference Digest; 02/2002
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    ABSTRACT: A novel low thermal budget (≤400°C) germanium MOS process with high-κ gate dielectric and metal gate electrode has been demonstrated. For the first time, self-aligned surface-channel Ge p-MOSFETs with ZrO<sub>2</sub> gate dielectric having equivalent oxide thickness (EOT) of 6-10 Å and platinum gate electrode are demonstrated with twice the low-field hole mobility of Si MOSFETs.
    Electron Devices Meeting, 2002. IEDM '02. International; 02/2002
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    ABSTRACT: Structural and electrical properties of gate stack structures containing ZrO2 dielectrics were investigated. The ZrO2 films were deposited by atomic layer chemical vapor deposition (ALCVD) after different substrate preparations. The structure, composition, and interfacial characteristics of these gate stacks were examined using cross-sectional transmission electron microscopy and x-ray photoelectron spectroscopy. The ZrO2 films were polycrystalline with either a cubic or tetragonal crystal structure. An amorphous interfacial layer with a moderate dielectric constant formed between the ZrO2 layer and the substrate during ALCVD growth on chemical oxide-terminated silicon. Gate stacks with a measured equivalent oxide thickness (EOT) of 1.3 nm showed leakage values of 10−5 A/cm2 at a bias of −1 V from flatband, which is significantly less than that seen with SiO2 dielectrics of similar EOT. A hysteresis of 8–10 mV was seen for ±2 V sweeps while a midgap interface state density (Dit) of ∼ 3×1011 states/cm eV was determined from comparisons of measured and ideal capacitance curves. © 2001 American Institute of Physics.
    Applied Physics Letters 04/2001; 78(16):2357-2359. · 3.79 Impact Factor
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    ABSTRACT: For the first time, we have successfully demonstrated the use of a high-κ gate dielectrics material ZrO2, for CMOS applications on pure germanium substrate. A near room temperature UV ozone oxidation technique has been developed for the formation of ZrO2. We have achieved excellent C-V characteristics with hysteresis of 1.5 mV and a capacitance-based equivalent SiO 2 thickness (tox,eq) of about 6-10 Å. A novel low thermal budget (= 400ºC) germanium MOS process with high- κ gate dielectric and metal gate electrode has been demonstrated. For the first time, self-aligned p-type surface- channel Ge MOSFETs with ZrO2 gate dielectric and platinum gate electrode are demonstrated in a conventional MOSFET structure with twice the low-field hole mobility than that for Si MOSFETs. The surface passivation makes it possible to fabricate metal- Ge-metal (MSM) integrated optical detectors for optical interconnect applications.
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    ABSTRACT: We report on experimental studies of the interfaces formed between high-k metal oxide dielectrics and silicon and germanium (100) substrates. In one case, an oxygen-gettering Ti overlayer was used to decompose the SiO2 interface layer (IL) initially present between HfO2 films and Si, thus reducing the gate stack equivalent oxide thickness (EOT) after high-k deposition. The mechanism of SiO2 decomposition is described and electrical results obtained from MOSCAP structures are reported. In a second set of experiments, ZrO2/Ge and HfO2/Ge interfaces were systematically probed by photoelectron spectroscopy and transmission electron microscopy (TEM). Although it was possible to obtain chemically-abrupt interfaces by direct deposition of high-k metal oxide films onto Ge, capacitance-voltage (CV) measurements indicated significant charge trapping and high interface state density for stacks with no interface layer. We found that thermal nitridation to create a GeOxNy IL prior to high-k deposition significantly improved the capacitor electrical characteristics. Finally, spectroscopic determination of the band offsets between HfO2 and GeOx IL and a Ge substrate is reported.