A. Emira

Cairo University, Al Qāhirah, Al Qāhirah, Egypt

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Publications (20)17.39 Total impact

  • [Show abstract] [Hide abstract]
    ABSTRACT: In this paper, two high-voltage charge pumps (CPs) are introduced. In order to minimize the area of the pumping capacitors, which dominates the overall area of the CP, high-density capacitors have been utilized. Nonetheless, these high-density capacitors suffer from low breakdown voltage, which is not compatible with the targeted high-voltage application. To circumvent the breakdown limitation, a special clocking scheme is used to limit the maximum voltage across any pumping capacitor. The two CP circuits were fabricated in a 0.6- μm CMOS technology with poly0-poly1 capacitors. The output voltage of the two CPs reached 42.8 and 51 V, whereas the voltage across any capacitor did not exceed the value of the input voltage. Compared with other designs reported in the literature, the proposed CP provides the highest output voltage, which makes it more suitable for tuning MEMS devices.
    IEEE Transactions on Industrial Electronics 01/2013; 60(10):4683-4693. · 6.50 Impact Factor
  • S Abdelaziz, A. M. Soliman, A. A. Emira
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    ABSTRACT: In thermoelectric scavenging systems, thermal energy is harvested from the temperature difference between the human body and the surrounding environment and converted into electric energy. Charge pumps are widely used in this purpose to increase the thermoelectric generator output voltage to a suitable voltage that can supply the standard integrated circuit. In this thesis a low-startup voltage charge pump which can operate with input voltages as low as 300mV is presented. The proposed charge pump architecture is the same as pelliconi but PMOS transistors are replaced with NMOS diode-connected transistors due to their low threshold voltage. An auxiliary circuit is added to each diode-connected NMOS transistor to cancel its threshold voltage drop. The output stage of the proposed charge pump is optimized to avoid the problems associated with diodeconnected configuration. Compared to the conventional charge pump techniques, the proposed technique is shown to offer lower output equivalent resistance and hence higher power efficiency and voltage gain. The proposed charge pump is suitable for energy harvesting applications due to its high efficiency and the ability of working at low voltage levels.
    2013 01/2013; Lap-Publisher Lambert Academic Publishing GmbH & Co. KG., ISBN: 978-3-8443-8498-7
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    ABSTRACT: In this paper, an efficient ultra-low-voltage PMU working for TEG input voltages as low as 200mV is proposed. The PMU core, charging an energy buffer, employs a main DC/DC converter. It consists of a cascade of two Dickson-based charge pumps with a variable conversion factor and switching frequency. Feedback is provided from the load buffer by means of a current sensor to a control unit that maximizes the overall power transfer efficiency at low input voltages. System simulation results demonstrate a peak efficiency greater than 70% with a controller current consumption less than 2μA. The PMU core was simulated in Cadence environment using a UMC CMOS 180nm process and the layout of the basic core building blocks is presented. The fully-integreable design consumes an area of approximately 30mm2.
    IEEE International New Circuits and Systems Conference (NEWCAS); 06/2012
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    ABSTRACT: This letter demonstrates RF microelectromechanical systems (MEMS) fractal capacitors possessing the highest reported self-resonant frequencies (SRFs) in PolyMUMPS to date. Explicitly, measurement results show SRFs beyond 20 GHz. Furthermore, quality factors higher than 4 throughout a band of 1-15 GHz and reaching as high as 28 were achieved. Additional benefits that are readily attainable from implementing fractal capacitors in MEMS are discussed, including suppressing residual stress warping, eliminating the need for etching holes, and reducing parasitics. The latter benefits were acquired without any fabrication intervention.
    Journal of Microelectromechanical Systems 01/2012; 21(1):10-12. · 2.13 Impact Factor
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    ABSTRACT: This paper studies analytically and numerically the spring softening and hardening phenomena that occur in electrostatically actuated microelectromechanical systems comb drive resonators utilizing folded suspension beams. An analytical expression for the electrostatic force generated between the combs of the rotor and the stator is derived and takes into account both the transverse and longitudinal capacitances present. After formulating the problem, the resulting stiff differential equations are solved analytically using the method of multiple scales, and a closed-form solution is obtained. Furthermore, the nonlinear boundary value problem that describes the dynamics of inextensional spring beams is solved using straightforward perturbation to obtain the linear and nonlinear spring constants of the beam. The analytical solution is verified numerically using a Matlab/Simulink environment, and the results from both analyses exhibit excellent agreement. Stability analysis based on phase plane trajectory is also presented and fully explains previously reported empirical results that lacked sufficient theoretical description. Finally, the proposed solutions are, once again, verified with previously published measurement results. The closed-form solutions provided are easy to apply and enable predicting the actual behavior of resonators and gyroscopes with similar structures.
    Journal of Microelectromechanical Systems 09/2011; · 2.13 Impact Factor
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    ABSTRACT: In this paper, an ultra-low-voltage charge pump is presented. Two techniques are used to reduce required number of stages and improve power efficiency, namely clock boosting and Vt cancellation. Clock boosting is employed to increase the output voltage per stage resulting in lower number of stages, and hence smaller output resistance. Vt cancellation is achieved by using an auxiliary circuit that enables the charge pump to operate at input voltages as low as 300mV. Compared to conventional charge pump techniques, the proposed technique is shown to offer higher power efficiency and voltage gain. The charge pump is designed using TSMC 0.25 µm CMOS technology.
    01/2011;
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    ABSTRACT: In this paper an integrated SAW-less narrowband RF front-end for direct conversion wireless receivers is presented. The analysis of the feedback system shows a shift of the center frequency f<sub>RX</sub> for the overall RF bandpass filter from its nominal value f<sub>LO</sub>. The proposed architecture incorporates a notch filter at 2f<sub>LO</sub> to insure that there is no shift in f<sub>RX</sub>. The design has been implemented in 65nm CMOS process. It consumes 44mA from a single 1.2V supply. Simulation results show a rejection of more than 15dB in a bandwidth of +/-500MHz around 2GHz due to the additional feedback loop. The theoretical and simulation results are in close agreement.
    Circuits and Systems (MWSCAS), 2010 53rd IEEE International Midwest Symposium on; 09/2010
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    ABSTRACT: A CMOS variable gain driving circuit with output signal amplitude control for gyroscopes with wide range of quality factors is presented. The driving circuit can be used for gyroscopes with Q values higher than 500. The circuit uses a current-commutating switching mixer to control the gyroscope driving signal level. Conventional driving circuits use automatic gain control (AGC) which suffers from limited linear range and the need for an off-chip capacitor for the peak detector and loop filter. Two stage variable gain amplifier is used in the proposed design to ensure enough gain for oscillation for such a wide range of quality factors. Analog and digital amplitude control methods are used to cover wide range of driving signal amplitude with enough accuracy to hit the maximum driving signal level without sacrificing gyroscope linearity. Due to the high DC gain of the amplifier chain, DC offset resulting from mismatches might saturate the amplifier output. DC offset correction is employed using a secondary negative feedback loop. The proposed driving circuit is being fabricated in 0.6 μm CMOS technology.
    Circuits and Systems (MWSCAS), 2010 53rd IEEE International Midwest Symposium on; 09/2010
  • M. Omar, A. Emira, M. Dessouky
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    ABSTRACT: This paper presents a novel VGA (Variable Gain Amplifier) with an embedded analog FIR (Finite Impulse Response) filter architecture. The idea is based on a modified version of the integrate and dump circuit. The proposed modifications allow altering the frequency response of the circuit without significantly increasing the circuit complexity along with maintaining acceptable gain control range, noise and linearity. The proposed circuit was designed using 0.13 μm CMOS technology. It consumes 105 μA from 1.2 V supply with an input referred noise of 27.15 nV/√(Hz).
    NEWCAS Conference (NEWCAS), 2010 8th IEEE International; 07/2010
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    ABSTRACT: In this work, a complete single-ended readout circuit for capacitive MEMS gyroscope using chopper stabilization technique is presented. A novel noise cancellation technique is used to get rid of the bias noise. The circuit offers superior performance over state of the art readout circuits in terms of cost, gain, and noise for the given area and power consumption. The full circuit exhibits a gain of 58dB, a power dissipation of 1.3mW and an input referred noise of 12nV/√Hz. This would significantly improve the overall sensitivity of the gyroscope. The full circuit has been fabricated in 0.6μm CMOS technology and it occupies an area of 0.4mm × 1mm.
    NEWCAS Conference (NEWCAS), 2010 8th IEEE International; 07/2010
  • A. Emira, H. Elwan, S. Abdelaziz
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    ABSTRACT: In this paper, an integrated DC-DC (Buck) converter is presented. The Buck converter has two modes of operation. The continuous mode is used for heavy loads, and the pulse-skipping modulation (PSM) mode is used for light loads. To optimize the Buck converter efficiency in PSM mode, an ON-time control loop is utilized. Short-circuit and over-temperature protection schemes are used to improve the design robustness. Three Buck converters were integrated in a TSMC 0.25μm CMOS chip with 2×2mm<sup>2</sup> die area. Up to 93% and 86% efficiencies are achieved at 2.5V and 1.2V output, respectively, using 3.6V input.
    Circuits and Systems (ISCAS), Proceedings of 2010 IEEE International Symposium on; 07/2010
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    ABSTRACT: This brief proposes a scalable multichannel clock and data recovery architecture that exploits the synchrony of multiple point-to-point serial links and uses a single voltage-controlled oscillator (VCO) to drive multiple phase detection loops. The proposed architecture can be naturally reduced by design to an ensemble of weakly interacting delay-locked loops. As a result, the jitter peaking problem is asymptotically eliminated, which makes this architecture well suited for use in long-haul repeater chains. Moreover, it allows controlling VCO jitter transfer to the recovered clock without affecting data jitter transfer. The architecture is demonstrated both by a Verilog-A behavioral model along with a rigorous system and statistical analysis.
    Circuits and Systems II: Express Briefs, IEEE Transactions on 06/2010; · 1.33 Impact Factor
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    ABSTRACT: A two-stage differential-ramp based continuous-tuning IF VGA is introduced. The design has a bandwidth in excess of 100 MHz consuming 5-mA from a 1.2-V supply. The ramp generation circuit consumes additional 200 muA from a 2.5-V supply. Thanks to the multiple differential control ramps, 49-dB linear-in-dB continuous gain tuning range is achieved with 19-dBm OIP3 at the maximum gain setting. The input referred noise density of the proposed design at maximum gain setting of 40-dB is 3.5-nV/sqrt(Hz).
    Circuits and Systems, 2009. ISCAS 2009. IEEE International Symposium on; 06/2009
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    ABSTRACT: A unified system-level design methodology for highly integrated CMOS radio frequency receiver design is introduced. This complete system-level design methodology is targeted to minimize the total power consumption of the receiver. System-level design techniques which can be used to derive the overall receiver radio specifications and study noise and linearity performance of receivers are presented. Then, a few circuit examples of building blocks in receiver signal chain are analyzed to show a linear relationship between power and dynamic range of the blocks. The result is then used to derive the optimal system specification distribution among receiver signal chain building blocks yielding the minimum total receiver power consumption for a given system performance. The theory and an actual CMOS Bluetooth receiver design are compared showing very good agreement.
    Circuits and Systems I: Regular Papers, IEEE Transactions on 06/2006; · 2.24 Impact Factor
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    ABSTRACT: A 12th order OTA-C complex filter with a non-conventional frequency tuning for Bluetooth receiver is implemented in a low-cost mainstream 0.35 μm CMOS process. The filter bandwidth is 1 MHz and is centered at 2 MHz. Image and adjacent channels are attenuated by 45 and 27 dB, respectively. The input referred noise is 29 μV<sub>rms</sub> and it dissipates 4.7 mA from a 2.7 V supply. Experimental results were found to be in good agreement with theoretical expectations.
    Circuits and Systems, 2003. ISCAS '03. Proceedings of the 2003 International Symposium on; 06/2003
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    ABSTRACT: A low-power quadrature direct digital frequency synthesizer (DDFS) is presented. Piecewise linear approximation is used to avoid using ROM lookup table to store the sine values. ROM elimination has resulted in significant power and area savings. The proposed DDFS has been implemented using 0.5µm CMOS process and occupies 1.4mm<sup>2</sup>area. It achieves an extremely low power consumption of only 8mW at 100MHz and operates from a single 2.7V supply. The SFDR is better than 58dBc at low synthesized frequencies and the frequency resolution is 1.5kHz.
    Solid-State Circuits Conference, 2002. ESSCIRC 2002. Proceedings of the 28th European; 10/2002
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    ABSTRACT: This paper presents a monolithic low-IF Bluetooth receiver. The highlights of the receiver include a low-power active complex filter with a non-conventional tuning scheme and a high performance mixed-mode GFSK demodulator. The chip was fabricated on a 6.25 mm<sup>2</sup> die using TSMC 0.35 μm standard CMOS process. -82 dBm sensitivity at 1e-3 BER, -10 dBm IIP3 and 15 dB noise figure were achieved In the measurements
    Radio Frequency Integrated Circuits (RFIC) Symposium, 2002 IEEE; 02/2002
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    ABSTRACT: The design of current mirror involves different conflicting design specifications (noise, bandwidth, input and output resistances, power dissipation, accuracy, THD, etc..), while only three design transistor parameters are available (DC current, width, length). In this paper, we address the effect of such parameters on the current mirror performance. For each specification, an expression is derived which is valid for any inversion level based on the one-equation for all-region MOS model. Experimental results from a current mirror fabricated in 0.5μm AMI CMOS process are found in good agreement with the theoretical ones.
    Circuits and Systems, 2002. ISCAS 2002. IEEE International Symposium on; 02/2002
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    ABSTRACT: A fully integrated low-IF CMOS Bluetooth receiver is presented. The IC is fabricated in TSMC 0.35 μm standard CMOS process. The receiver consists of a radio frequency (RF) front end, a phase lock loop (PLL), an active complex filter, a GFSK demodulator and a frequency offset cancellation circuit. The experimental results show a -82 dBm sensitivity at le-3 BER, -10 dBm IIP3 and 15 dB noise figure.
    Custom Integrated Circuits Conference, 2002. Proceedings of the IEEE 2002; 02/2002
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    ABSTRACT: This paper presents the implementation of an incremental A/D converter for a power supply voltage of ±1 V. The design relies on using floating gate technique in order to reduce the effect of nonlinear settling due to possible saturation of the input stage and to achieve good performance under low voltage operation. The converter has been implemented in 0.5 μm CMOS technology with V<sub>TN</sub>=0.65 V and V<sub>TP</sub>=-0.90 V. The chip prototype occupies an area of 0.2 mm<sup>2</sup>. The converter has been designed for 15 bits of accuracy. Due to the limited accuracy of the measurement equipment, we were able to measure 11 bits of resolution. The converter operates at a clock frequency of 500 kHz and consumes less than 1 mW.
    Circuits and Systems, 2002. ISCAS 2002. IEEE International Symposium on; 02/2002

Publication Stats

91 Citations
17.39 Total Impact Points

Institutions

  • 2013
    • Cairo University
      • Department of Electronics and Communication Engineering
      Al Qāhirah, Al Qāhirah, Egypt
  • 2009
    • University of California, Santa Cruz
      • Department of Electrical Engineering
      Santa Cruz, California, United States
  • 2002–2006
    • Texas A&M University
      • Department of Electrical and Computer Engineering
      College Station, TX, United States