Frederic Rousseau

Publications (2)0 Total impact

• Source

  Available from: Virginie Fresse

  Conference Proceeding: Case study: deployment of the 2D NoC on 3D for the generation of large emulation platforms

  Virginie Fresse, Zhiwei Ge, Junyan Tan, Frederic Rousseau
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  ABSTRACT: The evaluation of Network-On-Chip (NoC) architectures is an up to date problem in the design of System-on-Chip. Emulation on FPGA (Field Programmable Gate Array) is used to cover all possible NoC solutions in a reduced exploration time. Emulation requires multi-FPGA platform as the resources for large NoC is important and cannot be handling by one FPGA. In the same time, SoC community is exploring 3D technology for the next generation of large SoC with 3D NoC, making emulation more complex. This paper presents a case study of the deployment of the 2D NoC structure to 3D. A design flow is proposed for the automatic generation of a NoCtargeting3D on multi-FPGAs. The flow integrates emulation blocks used for the validation and exploration on the NoC. With this automatic aided tool, the designer can evaluate and explore the NoC architecture and extract performances of the NoC regardless of the multi-component platform. One may expect a communication performance improvement using an adapted partitioning of the NoC, as highlighted by the results given in this paper.
  Rapid System Prototyping, Tampere Finland; 10/2012
• Source

  Available from: Ahmed Jerraya

  Article: An Optimal Memory Allocation for Application-Specific Multiprocessor System-on-Chip

  Samy Meftali, Ferid Gharsalli, Frederic Rousseau, Ahmed A. Jerraya
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  ABSTRACT: In this paper, we present a novel and systematic approach for the design of shared memory architectures in the case of applicationspecific multiprocessor system-on-chip. This paper focuses on a memory allocation step which is based on an integer linear programming model. It permits to obtain an optimal distributed shared memory architecture minimizing the global cost to access the shared data in the application, and the memory cost. Our approach allows automatic generation of an architecture-level specification of the application. The effectiveness of this approach is illustrated by a packet routing switch example.
  01/2002;