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ABSTRACT: A novel three-stage amplifier topology for low- voltage and large capacitive load applications is proposed. This scheme is called the dual-active capacitance in reversed nested miller compensation (DACRNMC). The frequency bandwidth of the DACRNMC amplifier is improved due to the usage of active compensation capacitors. The amplifier's die area is reduced compared to the existing techniques in reversed nested miller compensation (RNMC) scheme. Moreover, the presence of two left-half-plane zeros in the amplifier's frequency response enhances the stability and hence improves the settling behavior of the amplifier. The circuit level simulation results of the proposed amplifier with a 0.18 mum standard CMOS process achieve 20 MHz unity gain bandwidth and 59 degree phase margin, while driving 500 pF load from a single 1.5 V power supply.
Circuits and Systems, 2008. ISCAS 2008. IEEE International Symposium on; 06/2008
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ABSTRACT: This paper presents a reversed single active Miller compensation (RSAMC) technique for low-voltage and large capacitive load three-stage amplifiers. In this scheme, only one active compensation capacitor is employed. The main advantages of the proposed compensation method are the enhanced unity gain bandwidth and reduced silicon die area of the amplifier compared to those of the existing proposed techniques in reversed nested Miller compensation (RNMC) scheme. The simulation results with a 0.18 mum standard CMOS process achieve 27 MHz unity gain bandwidth and 60 degree phase margin for the proposed RSAMC amplifier, while driving 500 pF load from a single 1.5 V power supply.
Circuits and Systems, 2008. ISCAS 2008. IEEE International Symposium on; 06/2008
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ABSTRACT: This paper presents an accurate and simple model for dc gain nonlinearity of operational amplifiers used in the switched-capacitor circuits such as the sigma-delta modulators. The proposed model can simply be used in the time-domain system level simulation of sigma-delta modulators to evaluate the effect of amplifier's dc gain nonlinearity on the overall linearity of the modulator as well as in the other switched- capacitor circuits as explored in the paper.
Circuit Theory and Design, 2007. ECCTD 2007. 18th European Conference on; 09/2007
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ABSTRACT: This paper presents novel double sampling high-order single loop sigma-delta modulator structures for wide-band applications. To alleviate the quantization noise folding into the inband frequency region, two previously reported techniques are used. The digital-to-analog converter's sampling paths are implemented with the single-capacitor approach and an additional zero is placed at the half of the sampling frequency of the modulator's noise transfer function (NTF). The detrimental effect of this additional zero on both the NTF and signal transfer function is also resolved through the proposed modulator architectures with a low additional circuit requirement.
Circuits and Systems II: Express Briefs, IEEE Transactions on 05/2006; 53(4):314- 318. · 1.41 Impact Factor
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ABSTRACT: This brief presents a time-domain model for the slew rate of CMOS two-stage Miller compensated operational transconductance amplifiers. The effects of both the first- and second-stage currents are considered in this model and a simple analytical expression is given in terms of the compensation and load capacitors, output voltage change, and device sizes. HSPICE simulation results are provided to show the validity of the proposed model using a 0.25-μm CMOS technology.
Circuits and Systems II: Express Briefs, IEEE Transactions on 04/2005; · 1.41 Impact Factor
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ABSTRACT: The authors present a new fully differential operational transconductance amplifier (OTA) for low-voltage and fast-settling switched-capacitor circuits in pure digital CMOS technology. The proposed two-stage OTA is a hybrid class A/AB that combines a folded cascode as the first stage with active current mirrors as the second stage. Owing to the class AB operation in the second stage, slew limiting occurs only in the first stage, resulting in low power dissipation for switched -capacitor circuits. It employs a novel hybrid cascode compensation scheme, merged Ahuja and improved Ahuja style compensations, for fast settling. A design procedure for the minimum settling time of the proposed OTA is described. To demonstrate the efficiency of the proposed OTA and its compensation method three design examples are also provided.
IEE Proceedings - Circuits Devices and Systems 01/2005; · 0.36 Impact Factor
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ABSTRACT: This paper presents a complete time-domain model for the slewing behavior of CMOS two-stage operational transconductance amplifiers (OTAs). In this model, the effects of both first and second stage currents are included. An analytical expression is given in terms of the compensation capacitance, load capacitance and device sizes for each positive and negative slew rates. HSPICE simulation results are provided to show the validity of the proposed models using a 0.35-μm CMOS technology. These models show near perfect agreement with simulation results.
Circuits and Systems, 2004. ISCAS '04. Proceedings of the 2004 International Symposium on; 06/2004
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ABSTRACT: This paper proposes a class of sigma-delta modulator topologies for low-voltage, high-speed, and high-resolution applications with low oversampling ratios (OSRs). The main specifications of these architectures are the reduced analog circuit requirements, large out-of-band gain in the noise transfer function (NTF) without any stability concerns to achieve high signal to noise ratio (SNR) with a low OSR, and unity-gain signal transfer function (STF) to reduce the harmonic distortions resulted from the analog circuit imperfections.
Circuits and Systems, 2004. ISCAS '04. Proceedings of the 2004 International Symposium on; 06/2004
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ABSTRACT: In this paper a study on different architectures of IF receivers is presented. Existing architectures are compared to suggest the most suitable one for low-voltage low-power wireless applications. Due to limitation of portable equipments, e.g. limited battery life, the main focus lies on the power consumption and integration capability. To have a more practical comparison, the feasibility of removing unnecessary blocks as well as integrating external blocks and components are investigated.
Electronics, Circuits and Systems, 2003. ICECS 2003. Proceedings of the 2003 10th IEEE International Conference on; 01/2004
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ABSTRACT: This paper presents a new compensation method for fully differential two-stage CMOS operational transconductance amplifiers (OTAs). It employs a hybrid cascode compensation scheme, merged Ahuja and improved Ahuja style compensations, for fast settling. A design procedure for minimum settling time of the proposed compensation technique for a two-stage class A/AB OTA is described. To demonstrate the usefulness of it, three design examples are considered.
Electronics, Circuits and Systems, 2003. ICECS 2003. Proceedings of the 2003 10th IEEE International Conference on; 01/2004
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ABSTRACT: In this paper a very low-noise low-power correlated double sampled integrator has been presented. For attenuating the sampling thermal noise, two large capacitors are incorporated in the integrator without using the large sampling and integrating capacitors that are necessary in ordinary integrators. The integrator is used in the front-end of a 24 bit, fourth-order single-loop single-bit delta-sigma modulator with a bandwidth of 1000 rad/s. A fully differential class AB op-amp with a preamplifier is designed with gain of 85 dB, bandwidth of 12 Mrad/s and overall input referred noise floor of -171 dB without the need for large compensation capacitors as in the ordinary topologies are used. The integrator power consumption is only 2.8 mW with a single 3.0 V supply in 0.6-μm CMOS technology.
Electronics, Circuits and Systems, 2003. ICECS 2003. Proceedings of the 2003 10th IEEE International Conference on; 01/2004
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ABSTRACT: This paper presents a 1.2 V, 1.6 mW and high-resolution sigma-delta modulator for digital audio. It uses a modified low-swing integrator output 4<sup>th</sup> order single loop topology. Modulator coefficients have been optimized for higher overload level factor and low power. A low-power two-stage class A/AB OTA with modified common mode feedback (CMFB) circuit in the first stage has been used in the first integrator. For reducing the power consumption, a simple folded-cascode OTA has been used in the last three integrators. Simulation results with an OSR of 100 give SNDR and dynamic range (DR) of 99.5 dB and 107 dB, including the circuit noise in the 25 kHz signal bandwidth, respectively. The circuit is implemented in a 0.25 μm standard CMOS technology.
Circuits and Systems, 2003. ISCAS '03. Proceedings of the 2003 International Symposium on; 06/2003
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ABSTRACT: This paper describes a 10-bit 150 MS/s CMOS parallel pipeline ADC. The converter includes four parallel interleaved pipeline A/D converters with analog background calibration using adaptive signal processing, an extra channel, and mixed signal integrators that match the offsets and gains of time-interleaved ADC channels. With monolithic analog background calibration, the SNDR in all corner cases (SS, SF, FS, FF, and TT) and temperature between -40°C to 85°C is better than 57 dB. The power consumption is 1200 mW at a 3.0 V supply voltage. This work is achieved in a 0.6 μm CMOS process.
Circuits and Systems, 2002. ISCAS 2002. IEEE International Symposium on; 02/2002
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ABSTRACT: This paper proposes a behavioral simulation of a wideband, 1.25 MHz, six-order, two-path, double-sampled, bandpass, sigma-delta modulator at IF-frequency 40 MHz with 78 dB dynamic range in a 0.35 μm CMOS process.
Circuits and Systems, 2002. APCCAS '02. 2002 Asia-Pacific Conference on; 02/2002
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ABSTRACT: This paper presents a 3.3-V, 18-bit Sigma-Delta modulator for digital audio, which has been simulated in a 0.6 μm double poly, triple metal CMOS process using poly-poly capacitors in all process corners and considering ± 10 % power supply and -40°C to 85°C temperature ranges. The integral gain coefficients of a 2-2 cascaded modulator have been developed for achieving higher overload level factor that is needed for high-resolution noise limited performance modulators. Simulation results give SNDR of 111 dB and 110 dB in typical and worst case, respectively with considering of the circuit noise.
Circuits and Systems, 2002. ISCAS 2002. IEEE International Symposium on; 02/2002
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ABSTRACT: This paper discusses the architecture and circuit requirements for a CMOS sigma-delta modulator that provides digital audio performance. The performance objective is to achieve a dynamic range of 110 dB (18-bit resolution) for a 25 kHz signal bandwidth while operating from a single 3.3 V power supply.
Microelectronics, 2001. ICM 2001 Proceedings. The 13th International Conference on; 11/2001
