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IEEE Transactions on Electron Devices 04/2012; 59(4):878-887. · 2.32 Impact Factor
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Proc. 13th Int. Symp. on Quality Electronic Design (ISQED'12), San Jose; 03/2012
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ABSTRACT: Density of STT-RAMs is limited by the area cost and width of the access device in a cell since it needs to support the programming currents. This paper explores a cell structure that shares each cell's access transistor with multiple MTJ memory elements. Feasibility and limitations of such a cell structure is explored for both reading and writing of the memory. The analytical and simulation results indicate that only small amount of sharing is possible and having MTJs that can handle a high read current without disturbing the cell is needed.
Nanoscale Architectures (NANOARCH), 2011 IEEE/ACM International Symposium on; 07/2011
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ABSTRACT: This paper introduces a design-space feasibility region as a function of MTJ characteristics and memory target specifications. The sensitivity of the design space is analyzed for scaling of both MTJ and underlying transistor technology. Design points for improved yield, density, and memory performance can be extracted for 90nm down to 32nm processes based on measured MTJ devices. To achieve flash-like densities in upcoming 22nm and 16nm technology nodes, scaling of the critical switching current density is required.
Nanoscale Architectures (NANOARCH), 2011 IEEE/ACM International Symposium on; 07/2011
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ABSTRACT: The ten papers in this special issue focus on high-performance multichip interconnections. The papers span novel transmitter and receiver equalization and data-recovery architectures, channel architecture organizations, comparisons with optical transmission techniques, advanced signal processing and coding concepts, and network optimization.
Circuits and Systems II: Express Briefs, IEEE Transactions on 06/2010; · 1.41 Impact Factor
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ABSTRACT: This paper presents a digital phase-locked loop (DPLL) used for GHz clock generation in large digital systems with >100Ã range of operating frequency. The DPLL uses phase selection and interpolation as the digital-controlled oscillator (DCO). A bandwidth-tracking technique that uses replica delay cells in the DCO and the phase detector (PD) is introduced to enable stable operation across the frequency range without calibration. Measurement results show that the DPLL achieves an output frequency up to 1.8 GHz in a 65-nm CMOS technology. Nearly constant damping factor and the tracking of the loop bandwidth to reference frequency are shown with a dynamic sweep of 8Ã reference frequency range (from 28 MHz to 225 MHz with core frequency of 3.6 GHz).
IEEE Journal of Solid-State Circuits 05/2010; · 3.23 Impact Factor
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ABSTRACT: A method to minimize the supply sensitivity of a CMOS ring oscillator is proposed through joint biasing of the supply and the control voltage. The technique can supplement a number of common supply rejection techniques and can be exploited to compensate for the noise coupling caused by the parasitic capacitance in the loop filter of a phase-locked loop (PLL). The proposed CMOS ring oscillator is designed and implemented with a charge-pump based PLL in 65-nm technology to demonstrate the robustness against the supply fluctuation. Taking advantage of the negative static supply sensitivity of the ring oscillator with proper combination of the bias voltages, the rms jitter of the 5.12-GHz output clock is reduced from 6.41 ps to 2.38 ps while subject to supply noise at 90 MHz.
IEEE Journal of Solid-State Circuits 10/2009; · 3.23 Impact Factor
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ABSTRACT: A 5-bit 4.8 GS/s 4-way time-interleaved ADC is designed for a receiver front-end in a 0.13 mum CMOS technology. Each time-interleaved ADC uses look-ahead pipelined stages to enable higher sample rates and more linear residue characteristics than a conventional pipeline ADC. At 1.2 GHz per path, the residue amplifiers settle to 75% of their final value, however, the linear residue characteristics allows using digital reference calibration to enable 30.4 dB of SNDR with a 1.2 MHz input signal. A capacitor pre-charging technique reduces the memory effect errors of the incompletely settled residue to 2% of the stage output swing. The peak INL and DNL are measured as 0.65LSB and 0.55LSB, respectively. The measured ERBW is ~6.1 GHz. The ADC, including the reference buffers, consumes 300 mW from a 1.2-V supply while operating at 4.8 GHz conversion rate. A stage-by-stage feedback compensates the possible bandwidth limitation of the system using a per-stage speculative DFE. The DFE tap is adjustable between 0 and 0.4 using 8 control bits.
IEEE Journal of Solid-State Circuits 04/2009; · 3.23 Impact Factor
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ABSTRACT: This paper introduces a hybridized version of two common topologies of LC-based clock buffers. The proposed design can minimize jitter by adaptively adjusting the ratio between these two topologies. The analysis shows that the setting for optimum jitter depends on the relative level between the input noise and the inherent noise of the clock buffer. The long-term and short-term jitters are both studied and supported by measurement. A frequency tuning technique based on a voltage-swing digitizer is also demonstrated. The test chip is fabricated in a 1P8M 1.2-V 0.13-mum digital CMOS process. The power consumption of the proposed LC-based clock buffer is 12 mW.
IEEE Journal of Solid-State Circuits 04/2009; · 3.23 Impact Factor
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ABSTRACT: Limited channel bandwidth introduces inter-symbol interference (ISI) at both data and edge samples. In addition to the ISI at data samples, ISI at the edge samples (edge ISI) increases the bit error rate (BER) by degrading on the eye diagram and increasing the jitter of the clock and data recovery (CDR). This work proposes a forward FIR equalizer and a decision-feedback equalizer (DFE) that compensate for both data and edge samples. To adapt both the data and edge equalizers, a modified LMS adaptation algorithm is introduced to achieve convergence. A transmitter and receiver are implemented in 0.13 mum and 0.18 mum technologies respectively. The edge ISI is improved by 20% and the jitter is improved by 10% in measurement. The link operates over a 120<sup>''</sup> FR4 channel with 24 dB attenuation at Nyquist frequency, and the BER is below 10<sup>-14</sup> at 3.6 Gb/s.
IEEE Journal of Solid-State Circuits 10/2008; · 3.23 Impact Factor
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ABSTRACT: A new adaptation strategy of I/O link equalizers is presented based on minimizing the bit error rate (BER) as the objective function to maximize the receiver voltage margin. The adaptation strategy is verified in a 90-nm test chip on both the transmitter finite-impulse response filter (Tx-FIR) and the receiver decision-feedback equalizer (Rx-DFE). The performance is compared with the commonly used sign-sign least mean square (SS-LMS) adaptation and demonstrates significant improvements especially in the case of the Tx-FIR. This paper also demonstrates that in a highly attenuating system that contains both a Tx-FIR and Rx-DFE, using a Tx-FIR subject to peak output power constraint to compensate pre-cursor ISI is worse than solely using an Rx-DFE. The adaptation strategy is further applied to adapt the sampling phase of the clock-and-data recovery loop (CDR). The technique enables near-optimal BER performance by substantially reducing the pre-cursor ISI and requires almost no additional hardware compared to SS-LMS adaptation.
IEEE Journal of Solid-State Circuits 10/2008; · 3.23 Impact Factor
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ABSTRACT: The design and analysis of a large-swing transformer-boosted serial link transmitter is described. Transformer boosting is used to produce a signal swing that is not constrained by the supply voltage and enables a true pre-emphasis transmitter with a differential output swing greater than the supply. The boosted signal is separated from the driver through series inductors and therefore does not stress the transistor voltage tolerance. Several design tradeoffs between the amounts of boosting, power, and output matching are examined in both analysis and simulation. Distributed boosting is employed to relax the tradeoff between the amount of boosting and output matching degradation. Implemented in a 0.13-mum CMOS technology, the prototype chip produces an 8-Gb/s PRBS 2<sup>31</sup>-1 data pattern and achieves a 1.42 V<sub>pp</sub> differential output swing while drawing 137 mA current from a 1.2-V supply. The measured output reflection coefficient is better than -10dB up to 4 GHz
IEEE Journal of Solid-State Circuits 06/2007; · 3.23 Impact Factor
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ABSTRACT: A low-power receiver with a one-tap decision feedback equalization (DFE) was fabricated in 90-nm CMOS technology. The speculative equalization is performed using switched-capacitor-based addition at the front-end sample-hold circuit. In order to further reduce the power consumption, an analog multiplexer is used in the speculation technique implementation. A quarter-rate-clocking scheme facilitates the use of low-power front-end circuitry and CMOS clock buffers. The receiver was tested over channels with different levels of ISI. The signaling rate with BER<10<sup>-12</sup> was significantly increased with the use of DFE for short- to medium-distance PCB traces. At 10-Gb/s data rate, the receiver consumes less than 6.0 mW from a 1.0-V supply. This includes the power consumed in all quarter-rate clock buffers, but not the power of a clock recovery loop. The input clock phase and the DFE taps are adjusted externally
IEEE Journal of Solid-State Circuits 05/2007; · 3.23 Impact Factor
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ABSTRACT: A quarter-rate sampling receiver with a 2-tap decision feedback equalizer (DFE) is implemented in 90-nm CMOS technology for low-power I/O links. An analog sampling and soft-decision technique is introduced to relax the timing critical feedback path of the DFE. The shortened critical path enables better power performance. Error rates are below the measurement capability of 10<sup>-12</sup> with 2<sup>31</sup>-1 PRBS at 6 Gb/s, with an 80-mV differential launch amplitude through a channel with 6.2-dB attenuation at 3 GHz. The receiver draws 4.08 mA from a 1.0-V supply
IEEE Journal of Solid-State Circuits 05/2007; · 3.23 Impact Factor
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ABSTRACT: Phase-locked loops (PLLs) are a critical component in modern systems. Digital PLLs (DPLLs) are increasingly popular in CMOS technologies due to their ease of integration and scalability with digital logic. However, digital quantization results in larger steady-state systematic jitter, or dithering. High resolution is needed to control the oscillator to minimize the dithering. This brief proposes a simple method to reduce the frequency-resolution requirement. The method allows for substantial reduction in the hardware complexity without sacrificing the DPLL's dynamic characteristics
Circuits and Systems II: Express Briefs, IEEE Transactions on 04/2007; · 1.41 Impact Factor
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ABSTRACT: The design of a 600-MS/s 5-bit analog-to-digital (A/D) converter for serial-link receivers has been investigated. The A/D converter uses a closed-loop pipeline architecture. The input capacitance is only 170 fF, making it suitable for interleaving. To maintain low power consumption and increase the sampling rate beyond the amplifier settling limit, the paper proposes a calibration technique that digitally adjusts the reference voltage of each pipeline stage. Differential input swing is 400 mV<sub>p-p</sub> at 1.8-V supply. Measured performance includes 25.6 dB and 19 dB of SNDR for 0.3-GHz and 2.4-GHz input frequencies at 600 MS/s for the calibrated A/D converter. The suggested calibration method improves SNDR by 4.4 dB at 600 MS/s with ±0.35 LSB of DNL and ±0.15 LSB of INL. The 180 × 1500 μm<sup>2</sup> chip is fabricated in a 0.18-μm standard CMOS technology and consumes 70 mW of power at 600 MS/s.
IEEE Journal of Solid-State Circuits 03/2006; · 3.23 Impact Factor
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ABSTRACT: This paper demonstrates a multichannel multiphase sampling system using a 700-MHz operating frequency to produce a base sampling rate of 7 GSample/s for each channel in a typical 0.18-μm CMOS technology. An extra phase cluster with <10-ps sampling phase spacing is generated. To achieve this small phase spacing, static phase and voltage errors are digitally calibrated. Additionally, a redundancy technique is introduced in this paper to further halve the residual voltage error of the samplers. A third technique, i.e., "reference subtraction," is applied to remove cross-channel correlated dynamic noise. The resulting phase spacing is only limited by the uncorrelated random noise in the system. With this fine sampling phase resolution, this system has the ability to measure cycle-to-cycle jitter in real time.
IEEE Journal of Solid-State Circuits 02/2006; · 3.23 Impact Factor
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ABSTRACT: A 4-bit 6GS/s A/D converter is designed for a serial-link receiver and features an embedded adjustable one-tap DFE. Feedback-delay is relaxed through applying DFE to a 10-way interleaved pipelined architecture. Code-overlapping is used to remove residual ISI. Measured performance at 6GS/s shows 22.5dB of low-frequency input SNDR. DFE tap-coefficient is adjustable from 0 to 0.25 with 6-bits of programmable weight. The 1.8×1.6mm<sup>2</sup> chip is fabricated in 0.18μm CMOS technology and consumes 780mW at 1.8V power-supply.
VLSI Circuits, 2005. Digest of Technical Papers. 2005 Symposium on; 07/2005
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ABSTRACT: The resolution of a comparator is determined by the dc input offset and the ac noise. For mixed-mode applications with significant digital switching, input-referred supply noise can be a significant source of error. This paper proposes an offset compensation technique that can simultaneously minimize input-referred supply noise. Demonstrated with digital offset compensation, this scheme reduces input-referred supply noise to a small fraction (13%) of one least significant bit (LSB) digital offset. In addition, the same analysis can be applied to analog offset compensation.
IEEE Journal of Solid-State Circuits 06/2004; · 3.23 Impact Factor
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ABSTRACT: This paper describes a 3.6-Gb/s 27-mW transceiver for chip-to-chip applications. A voltage-mode transmitter is proposed that equalizes the channel while maintaining impedance matching. A comparator is proposed that achieves sampling bandwidth control and offset compensation. A novel timing recovery circuit controls the phase by mismatching the current in the charge pump. The architecture maintains high signal integrity while each port consumes only 7.5 mW/Gb/s. The entire design occupies 0.2 mm<sup>2</sup> in a 0.18-μm 1.8-V CMOS technology.
IEEE Journal of Solid-State Circuits 05/2004; · 3.23 Impact Factor
