P. Flatresse

Publications (10)1.45 Total impact

• Conference Proceeding: Power switch optimization and sizing in 65nm PD-SOI considering supply voltage noise

  J. Le Coz, A. Valentian, P. Flatresse, M. Belleville
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  ABSTRACT: In this paper, several power gating solutions are analysed in 65 nm PDSOI technology, taking into account the implementation area. A new figure of merit has been proposed to easily determine the best tradeoff between leakage, drive current and area. It shows that the best solution is to use a Body-Contacted transistor with a non-minimal gate length, enabling leakage currents of the same order of magnitude than in Bulk. A second analysis on specific PD-SOI Logic CORE electrical behaviour has been performed. This analysis allows determining the power switch network sizing implementation taking into account decoupling capacitance, ON Logic CORE current and equivalent parasitic supply inductance.
  IC Design and Technology (ICICDT), 2010 IEEE International Conference on; 07/2010
• Conference Proceeding: An accurate approach for statistical estimation of leakage current considering multi-parameter process variations in nanometer CMOS technologies

  C. D'Agostino, J. Le Coz, P. Flatresse, E. Beigne, M. Belleville
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  ABSTRACT: The dramatic increase in leakage current has become a major issue for future IC design. Moreover, as process variability in nano-scaled CMOS technologies induces a large spread of leakage power values, leakage variability cannot be neglected anymore. In this work an accurate analytic estimation and modeling methodology has been developed for CMOS circuit leakage under statistical process variations. The developed methodology is integrated with standard BSIM4 and PSP transistor model, and applicable to any CMOS technologies (90 nm, 65 nm, 45 nm), and SPICE simulators. Subthreshold, gate, BTBT, and GIDL leakage currents variations are considered. Comparisons with Monte-Carlo simulations on 45 nm STMicroelectronics CMOS technologies fully validate the accuracy and efficiency of the proposed method.
  Solid State Device Research Conference, 2009. ESSDERC '09. Proceedings of the European; 10/2009
• Conference Proceeding: Statistical leakage modeling in CMOS logic gates considering process variations

  C. D'Agostino, P. Flatresse, E. Beigne, M. Belleville
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  ABSTRACT: The dramatic increase in leakage current, coupled with the swell in process variability in nano-scaled CMOS technologies, has become a major issue for future IC design. Moreover, due to the spread of leakage power values, leakage variability cannot be neglected anymore. In this work an accurate analytic estimation and modeling methodology has been developed for logic gates leakage under statistical process variations. The developed methodology is completely based on BSIM4 equations, implemented in Verilog-A, and applicable to any different CMOS technologies (90 nm, 65 nm, etc), electrical simulators and models. For the first time subthreshold, gate, BTBT, and GIDL leakage variations are considered. Comparisons to Monte-Carlo simulation on 90 and 65 nm STMicroelectronics CMOS technologies fully validate the accuracy of the proposed method and demonstrate the efficiency of the proposed analysis method.
  Integrated Circuit Design and Technology and Tutorial, 2008. ICICDT 2008. IEEE International Conference on; 07/2008
• Article: SEU sensitivity of bulk and SOI technologies to 14-MeV neutrons

  G. Gasiot, V. Ferlet-Cavrois, J. Baggio, P. Roche, P. Flatresse, A. Guyot, P. Morel, O. Bersillon, J. du Port de Pontcharra
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  ABSTRACT: This work investigates the effects of 14-MeV neutron irradiation on bulk and silicon-on-insulator (SOI) technologies. Experimental results are reported with a study on the influence of the irradiation angle. These experiments are interpreted with a nuclear interaction code (MCNP: Monte Carlo N-Particle). The device architecture and the involved materials are shown to be determining parameters with respect to the device sensitivity.
  IEEE Transactions on Nuclear Science 01/2003; · 1.45 Impact Factor
• Conference Proceeding: History effect characterization in PD-SOI CMOS gates

  M.R. Casu, P. Flatresse
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  ABSTRACT: Partially depleted SOI CMOS gates with floating body exhibit variable propagation delays because of the history effect. In this paper we address the problem of how to find the steady-state in a CMOS gate without resorting to huge computer resources. Moreover, a simple method for the evaluation of delay upper and lower bounds is described.
  SOI Conference, IEEE International 2002; 11/2002
• Conference Proceeding: Converting an embedded low-power SRAM from bulk to PD-SOI

  M.R. Casu, P. Flatresse
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  ABSTRACT: The migration of an embedded 1 Mbit SRAM for low power applications from a 0.13μm bulk to a partially depleted silicon-on-insulator (PDSOI) technology is described in this paper. Floating body effects such as threshold voltage variation and parasitic bipolar turn on and their impact on sense amplifiers, pass-gates based multiplexers and dynamic decoders are addressed. Solutions like the use of body contacts in specific parts are discussed. A SRAM chip with various testable configurations has been taped out.
  Memory Technology, Design and Testing, 2002. (MTDT 2002). Proceedings of the 2002 IEEE International Workshop on; 02/2002
• Conference Proceeding: Comparison of the sensitivity to heavy ions of 0.25 μm bulk and SOI technologies

  G. Gasiot, V. Ferlet-Cavrois, P. Roche, P. Flatresse, C. D'hose, O. Musseau, J. du Port de Poncharra
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  ABSTRACT: The sensitivity to heavy ions of non-hardened 0.25 μm Partially Depleted (PD) SOI and bulk technologies is studied with experiments, device and circuit simulations. Comparable threshold LET are found for both technologies. Nevertheless, SOI saturated cross section is much lower than bulk one. For non-hardened technologies, SOI is then less sensitive than bulk to heavy ions.
  Radiation and Its Effects on Components and Systems, 2001. 6th European Conference on; 10/2001
• Conference Proceeding: Comparison of multiple cell upset response of BULK and SOI 130NM technologies in the terrestrial environment

  G. Gasiot, P. Roche, P. Flatresse
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  ABSTRACT: This paper presents alpha and neutron experimental results on 130 nm SRAMs processed in SOI and bulk technologies. Experiments were analyzed for multiple cells upset (MCU) occurrence. MCU percentages and rates were recorded as a function of different experimental parameters (supply voltage, test pattern, etc.). This work sheds light on the different mechanisms involved in MCU occurrence between SOI and bulk technologies.
  Reliability Physics Symposium, 2008. IRPS 2008. IEEE International;
• Conference Proceeding: A new and fast method to compute steady state in PD-SOI circuits and its application to standard cells library characterization

  V. Liot, P. Flatresse
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  ABSTRACT: In this paper, a fast and robust method to simulate the steady state equilibrium in Partially Depleted SOI circuits is described. This method is presented through the evaluation of the history effect in a 0.13 μm PD-SOI technology dedicated to low power/low voltage applications.
  SOI Conference, 2003. IEEE International;
• Conference Proceeding: Impact of CMOS Technology Scaling on SRAM Standby Leakage Reduction techniques

  O. Thomas, M. Belleville, F. Jacquet, P. Flatresse
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  ABSTRACT: This paper investigates leakage reduction techniques for a conventional 6T SRAM cell in advanced technologies. The most promising leakage reduction techniques that have been proposed are presented and compared for the 130-nm and 65-nm technology nodes. More specifically, the impact of the evolution of the gate tunneling and substrate currents is studied considering the efficiency of those techniques. Finally, the best techniques for leakage reduction in sub 100-nm SRAM cell, and guidelines on how to merge them in order to reach an optimum, are proposed
  Integrated Circuit Design and Technology, 2006. ICICDT '06. 2006 IEEE International Conference on;