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ABSTRACT: PFIX is a pixel architecture designed for colliding-beam
experiments at the Tevatron. Its most important application to date is
the BTeV experiment. PreFPIX2 is a chip designed to test the FPIX Core,
i.e., the pixel control and readout architecture. This FPIX Core will be
mated to a periphery specific to a particular experiment. Earlier plans
called for the BTeV FPIX chip to be designed in a rad-hard process.
However, deep-submicron CMOS processes have demonstrated appropriate
radiation tolerance at a lower cost and with greater reliability.
Therefore, PreFPIX2 has been fabricated in a 0.25 micrometer process
utilizing radiation tolerant design techniques. The architecture has
undergone substantial development from earlier versions of FPIX. Most
notable are the improvements to the column token passing scheme and to
the end-of-column logic. Extensive simulations were performed using both
SPICE and structural-level Verilog. Monte Carlo physics simulations of
the BTeV pixel detector at half, full and double the planned luminosity
were converted to Verilog compatible input files for the chip
simulations, allowing the designers to observe the chip operating under
real conditions and for extended periods of time. Analyzes of the
results reveal that at all luminosities the FPIX Core correctly
identifies better than 99.6% of input hits. Bench tests of fabricated
chips confirm the accuracy of the simulations
IEEE Transactions on Nuclear Science 07/2001; · 1.45 Impact Factor
