ABSTRACT: The exploration of vertically integrated circuits, also commonly known as 3D-IC technology, for applications in radiation detection started at Fermilab in 2006. This paper examines the opportunities that vertical integration offers by looking at various 3D designs that have been completed by Fermilab. The emphasis is on opportunities that are presented by through silicon vias (TSV), wafer and circuit thinning, and finally fusion bonding techniques to replace conventional bump bonding. Early work by Fermilab has led to an international consortium for the development of 3D-IC circuits for High Energy Physics. For the first time, Fermilab has organized a 3D MPW run, to which more than 25 different designs have been submitted by the consortium.
IEEE Transactions on Nuclear Science 09/2010; · 1.45 Impact Factor
ABSTRACT: At Fermilab, there is an ongoing pixel detector R&D effort for high energy physics with the objective of developing high performance vertex detectors suitable for the next generation of HEP experiments. The pixel module presented here is a direct result of work undertaken for the cancelled BTeV experiment. It is a very mature piece of hardware, having many characteristics of high performance, low mass and radiation hardness driven by the requirements of the BTeV experiment. The detector presented in this paper consists of three basic devices; the readout integrated circuit (IC) FPIX2A, the pixel sensor (TESLA p-spray) and the high density interconnect (HDI) flex circuit that is capable of supporting eight readout ICs. The characterization of the pixel multichip module prototype as well as the baseline design of the eight-chip pixel module and its capabilities are presented. The PCI test adapter (PTA) card used to characterize the pixel module prototypes is also presented. These prototypes were characterized for threshold and noise dispersion. The bump-bonds of the pixel module were examined using an X-ray inspection system. Furthermore, the connectivity of the bump-bonds was tested using a radioactive source (<sup>90</sup>Sr), while the absolute calibration of the modules was achieved using an X-ray source. This paper provides a view of the integration of the three components that together comprise the pixel multichip module
Nuclear Science Symposium Conference Record, 2005 IEEE; 11/2005
ABSTRACT: One of the challenges posed by calorimeters in high-energy physics experiments is digitizing wide dynamic range charge signals at high rate to a specified precision. One response to this challenge is the development of the QIE (charge integrator and encoder) concept. A QIE chip divides the input signal into multiple ranges, with each range integrating a scaled fraction of the signal. The range integrators are offset so that for any given signal magnitude, only one range will be selected as valid. The selected range integrator output is digitized to form a mantissa, and a digital code associated with that range forms an exponent. The resulting modified floating-point output format gives approximately constant measurement precision over a wide dynamic range. Floating-point converter designs are usually tailored for a specific application. A general description of the QIE concept shows how parameters are chosen to suit the application. The design of a mixed-signal chip that has been produced for a specific experiment is presented.
IEEE Journal of Solid-State Circuits 07/2004; · 3.23 Impact Factor
ABSTRACT: PFIX is a pixel architecture designed for colliding-beam
experiments at the Tevatron. Its most important application to date is
the BTeV experiment. PreFPIX2 is a chip designed to test the FPIX Core,
i.e., the pixel control and readout architecture. This FPIX Core will be
mated to a periphery specific to a particular experiment. Earlier plans
called for the BTeV FPIX chip to be designed in a rad-hard process.
However, deep-submicron CMOS processes have demonstrated appropriate
radiation tolerance at a lower cost and with greater reliability.
Therefore, PreFPIX2 has been fabricated in a 0.25 micrometer process
utilizing radiation tolerant design techniques. The architecture has
undergone substantial development from earlier versions of FPIX. Most
notable are the improvements to the column token passing scheme and to
the end-of-column logic. Extensive simulations were performed using both
SPICE and structural-level Verilog. Monte Carlo physics simulations of
the BTeV pixel detector at half, full and double the planned luminosity
were converted to Verilog compatible input files for the chip
simulations, allowing the designers to observe the chip operating under
real conditions and for extended periods of time. Analyzes of the
results reveal that at all luminosities the FPIX Core correctly
identifies better than 99.6% of input hits. Bench tests of fabricated
chips confirm the accuracy of the simulations
IEEE Transactions on Nuclear Science 07/2001; · 1.45 Impact Factor