Yijun Zhou

Institute for Infocomm Research, Tumasik, Singapore

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Publications (14)10.58 Total impact

  • Yijun Zhou, M.Y.-W. Chia
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    ABSTRACT: This paper describes a novel alternating and outphasing modulator for the generation and amplification of a linear modulation signal. The architecture requires a linear modulation signal to be represented as two outphasing signals with a constant envelope, which are alternating or switching at the input of two nonlinear amplifiers to produce a linear modulation signal. A power combiner can be employed to cancel the mixed components due to the switching. This will minimize the requirements of the output filter, and hence, simplified the design. This new modulation architecture is simple, and hence, is suitable for all-digital integration. The measurement results of the wideband code division multiple access signal are presented and compared with a conventional linear amplification with nonlinear components architecture.
    IEEE Transactions on Microwave Theory and Techniques 03/2010; · 2.23 Impact Factor
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    ABSTRACT: This paper introduces a 900 MHz distributed active transformer coupled outphasing power combiner. The distributed active transformer is applied as the impedance transformer and power combiner for the outphasing power amplifier. Compared to existing solutions, the new architecture owns the advantages of low loss and compact size. The proposed combiner is suitable for fully integrated RF outphasing power amplifier design.
    Microwave Conference, 2009. APMC 2009. Asia Pacific; 01/2010
  • Yijun Zhou, MY Chia, Chiew Kok Ang
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    ABSTRACT: A novel 900 MHz outphasing power amplifier using LDMOS transistors has been developed. It uses a distributed active transformer for high efficiency impedance transformation and lossless power combining. The current mode class-D amplification technique is applied to amplify constant envelope and outphasing signals. The outphasing power amplifier has been tested with the wideband code division multiple access signal (WCDMA) and the 900 MHz continuous wave (CW) signal. The proposed design is suitable for fully integrated power amplification on silicon.
    Ultra-Wideband (ICUWB), 2010 IEEE International Conference onUltra-Wideband (ICUWB), 2010 IEEE International Conference on; 01/2010
  • Yijun Zhou, M.Y.-W. Chia
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    ABSTRACT: This paper introduces a low-power ultra-wideband true root-mean-square power detector with a 0.13-mum CMOS process operating from 125 MHz to 8.5 GHz. The detector utilizes the MOS transistor's square-law characteristic in the strong inversion region to obtain the power information of the input RF signal, and its exponential characteristic in the weak inversion region to realize the linear-in-decibel output. Measured dynamic ranges are 20 dB at 125 MHz and 18 dB at 8.5 GHz, respectively, with tolerances of plusmn0.5-dB error. WiMedia-ultrawideband and wireless local area network 802.11a signals with different modulation techniques and data rates are measured. The integrated detector operates at 1.2-V supply voltage, and its static power consumption is 0.18 mW.
    IEEE Transactions on Microwave Theory and Techniques 06/2008; · 2.23 Impact Factor
  • Yijun Zhou, Jiren Yuan
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    ABSTRACT: This paper describes a CMOS current-folded direct digital RF quadrature modulator, which uses two 10-bit linear interpolation current steering digital-to-analog converters (DACs) and two current-folded double-balanced mixers. The attenuation of the DAC image components is significantly increased with linear interpolation, and the reconstruction filter is therefore eliminated. The DAC baseband differential current signals are fed to the mixer by current-folded structures, which realize the low voltage design and improve the linearity of the modulated RF signal. The chip has been implemented with a 0.35 μm, double-poly and triple-metal CMOS process.
    Radio Frequency integrated Circuits (RFIC) Symposium, 2005. Digest of Papers. 2005 IEEE; 07/2005
  • Source
    Yijun Zhou, Jiren Yuan
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    ABSTRACT: An 8-bit 100-MHz CMOS linear interpolation digital-to-analog converter (DAC) is presented. It applies a time-interleaved structure on an 8-bit binary-weighted DAC, using 16 evenly skewed clocks generated by a voltage-controlled delay line to realize the linear interpolation function. The linear interpolation increases the attenuation of the DAC's image components. The requirement for the analog reconstruction filter is, therefore, greatly relaxed. The DAC aims for the single-chip integration of a wireless transmitter. The chip was fabricated in a 3.3-V 0.35-μm double-poly triple-metal CMOS process. The core size of the chip is 0.67 mm × 0.67 mm, and the total power consumption is 54.5 mW with 3.3-V power supplies. The attenuation (in decibels) of image components is doubled compared with a conventional DAC.
    IEEE Journal of Solid-State Circuits 11/2003; · 3.06 Impact Factor
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    Yijun Zhou, Jiren Yuan
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    ABSTRACT: A highly integrated CMOS direct digital RF quadrature modulator, consisting of two 10-bit linear interpolation current steering digital-to-analog converters (DACs) and two Gilbert cell based mixers, is described. By employing linear interpolation, the attenuation of the DAC's image components is significantly increased, and the reconstruction filter is therefore eliminated. The DAC's differential current signals are directly sent to the mixer, which improves the linearity of the modulated RF signal. Measurement results on operations of 16 QAM and GSM are presented. This structure is suitable for system-on-chip (SOC) design.
    Solid-State Circuits Conference, 2003. ESSCIRC '03. Proceedings of the 29th European; 10/2003
  • Yijun Zhou, Jiren Yuan
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    ABSTRACT: This paper describes a low-distortion wide-band CMOS direct digital RF amplitude modulator, which uses a 10-bit linear interpolation current-steering digital-to-analog converter (DAC) and a Gilbert-cell-based mixer to generate an amplitude modulated RF signal directly. The linear interpolation increases the attenuation of the DAC's image components. The reconstruction filter is, therefore, eliminated. The DAC's differential current signals are directly sent to the mixer, which improves the linearity of the modulated RF signal. Thus, the RF transmitter structure is simplified, and the low distortion is achieved. This modulator is suitable for system-on-chip (SOC) design and is easily scalable. The chip was fabricated in a 0.35-μm 3.3-V double-poly triple-metal CMOS process. The core size of the chip is 0.52 mm×0.68 mm. With a 3.3-MHz modulation signal, a 50-MHz clock, and a 1-GHz carrier, the distortion components are below -53.81 dBc, and the attenuation of the image signal is 47.45 dB. The output power is -6.5 dBm, and the total power consumption is 159.8 mW.
    IEEE Journal of Solid-State Circuits 08/2003; · 3.06 Impact Factor
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    Yijun Zhou, Jiren Yuan
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    ABSTRACT: A 10-bit, 100-MHz CMOS linear interpolation digital-to-analog converter (DAC) is presented. It includes a 16-tap voltage controlled delay line and a 10-bit binary-weighted DAC with a time-interleaved structure. The linear interpolation not only increases the attenuation of the DAC's image components, but also reduces the glitch of the binary-weighted DAC. The requirement for the analog reconstruction filter is therefore greatly relaxed. The DAC is optimized for the single chip design of wire or wireless transmitters. The chip was fabricated in a standard 3.3 V, 0.35 µm, double-poly, triple-metal digital CMOS process. The core size of the chip is 0.49mm × 0.52mm, and power consumption is 86.5 mw in 3.3 V power supply. The attenuation of image components is doubled (dB) compared with the conventional DAC.
    Solid-State Circuits Conference, 2002. ESSCIRC 2002. Proceedings of the 28th European; 10/2002
  • Lixin Yang, Yijun Zhou, Jiren Yuan
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    ABSTRACT: This paper presents a new multiphase clock generator using direct interpolators. No feedback loop is required. A single-stage direct interpolation architecture is proposed. A 1/4 frequency divider and a short-circuit current suppression interpolator are developed to achieve the precise interpolation. The circuit was fabricated in a standard 0.35 μm, 3.3 V CMOS process. The multiphase clock generator can operate in a wide range of input clock frequencies from 500 MHz to 1 GHz.
    Circuits and Systems, 2002. MWSCAS-2002. The 2002 45th Midwest Symposium on; 09/2002
  • Source
    Yijun Zhou, Jiren Yuan
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    ABSTRACT: This paper describes a direct digital RF amplitude modulator, which uses a 10-bit linear interpolation current steering digital to analog converter (DAC) and a Gilbert cell mixer to generate an RF amplitude modulated signal directly. The linear interpolation increases the attenuation of the DAC's image components. The low pass filter (LPF) is eliminated, and the RF transmitter structure can be simplified. This modulator is suitable for realizing the system-on-chip design. The chip has been fabricated in a 0.35 μm, 3.3 V digital CMOS process.
    Circuits and Systems, 2002. ISCAS 2002. IEEE International Symposium on; 02/2002
  • Yijun Zhou, Jiren Yuan
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    ABSTRACT: This paper describes a low distortion wide band CMOS direct digital RF amplitude modulator, which uses a 10-bit linear interpolation current steering digital to analog converter (DAC) and a Gilbert cell based mixer to generate an amplitude modulated RF signal directly. The linear interpolation increases the attenuation of the DAC's image components. The low pass filter (LPF) is therefore eliminated, and the RF transmitter structure is simplified. This modulator is suitable for system-on-chip design. The chip has been fabricated in a 0.35 µm, 3.3 V digital CMOS process. When the transmission signal is at 3 MHz, the distortion components are below -54 dBc at 800 MHz and -49 dBc at 1.2 GHz, respectively. The image signals are below -45 dBc when the transmission signal is a 5.2 MHz.
    Solid-State Circuits Conference, 2002. ESSCIRC 2002. Proceedings of the 28th European; 01/2002
  • Lixin Yang, Yijun Zhou, Jiren Yuan
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    ABSTRACT: This paper introduces the design of a new multiphase clock generator with no feedback loop. A single-stage direct interpolation architecture is proposed. A 1/4 frequency divider and a short-circuit current suppression interpolator are developed to achieve the precise interpolation. The circuit has been fabricated in a standard 0.35 μm, 3.3 V CMOS process. The multiphase clock generator can operate in a wide range of input clock frequencies from 500 MHz to 1.5 GHz.
    01/2002;
  • Yijun Zhou, Jiren Yuan
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    ABSTRACT: This paper describes an 8-Bit, 100-MHz current steering CMOS low glitch interpolation digital to analog converter (DAC). It includes a 16-tap voltage controlled delay line and 8-Bit based linear interpolators, making the effective clock rate up to 1.6-GHz. With the linear interpolation, the requirement on the analog reconstruction filter is relaxed, and low glitch digital to analog conversion is achieved. The chip is fabricated with a 3.3 V, 0.35 μm digital CMOS process
    Circuits and Systems, 2001. ISCAS 2001. The 2001 IEEE International Symposium on; 06/2001

Publication Stats

79 Citations
10.58 Total Impact Points

Institutions

  • 2003–2010
    • Institute for Infocomm Research
      Tumasik, Singapore
  • 2001–2003
    • Lund University
      • Department of Electroscience
      Lund, Skane, Sweden