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ABSTRACT: Recently, high-resolution TDCs have gained more and more popularity due to their increasing implementation in digital PLLs, ADCs, jitter measurement and time-of-flight measurement units. Similar to ADCs, existing architectures of TDCs can be divided into several categories: flash TDCs, pipeline TDCs, and SAR TDCs. The highest achievable time resolution of a TDC is mainly limited by the CMOS gate delay. In order to achieve sub-gate-delay resolution, the Vernier method is commonly used. However, the mismatch problem caused by process variation limits its effectiveness, and the same holds for the time amplification method. The gated-ring-oscillator (GRO) method is introduced to achieve sub-ps time resolution, but it still requires an equivalent CMOS gate delay as low as 6ps. Upcoming applications in 4,h-generation nuclear reactors, space, and high-energy physics such as the large Hadron collider (LHC), require the TDC to achieve a high time resolution in harsh environments with high tem perature and radiation, where the threshold voltage, transconductance, and delay of a transistor undergo dramatic changes. In these cases, the high accu racy and robustness of the TDC need to be inherent to the design rather than by employing a fast CMOS technology.
Solid-State Circuits Conference Digest of Technical Papers (ISSCC), 2011 IEEE International; 03/2011
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ABSTRACT: A differential voltage amplifier with a gain-bandwidth product of 2.5Ghz and using adaptive biasing has been designed in a standard CMOS technology and assessed under radiation and temperature variations. The principle used in this ASIC will be employed in the design of a Gbps TIA with improved tolerance for γ-irradiation and temperature for an optical instrumentation (LIDAR) receiver aiming at operation in harsh environments. The voltage amplifier was tested under gamma radiation and features a gain degradation of merely 4.5% up to a total dose of 100kGy. In order to verify the radiation effects on the IC, the threshold voltage shift of the separate transistors has been investigated. Temperature characterization has shown that the amplifier features a reduction of the voltage gain by only 5.6% for a temperature range of -40 till 130 °C.
Journal of Instrumentation 01/2011; 6(01):C01076. · 1.87 Impact Factor
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ABSTRACT: This paper presents an application of the VHDL-AMS modelling language to the characterisation of γ-radiation effects on bipolar transistors. The model is based on the Gummel-Poon bipolar transistor model and takes the radiation induced effects into account on parameter level. It is shown that the γ-radiation induced effects on the transistor's performance can be modelled by implementing a specific set of model parameters as dose dependent functions. Two different devices were modelled with this approach, a COTS matched pair bipolar transistor and a commercially available 0.35μm SiGe BiCMOS process. It is shown that both devices can be modelled within reasonable accuracy with the proposed VHDL-AMS radiation aware bipolar transistor model.
Radiation and Its Effects on Components and Systems (RADECS), 2009 European Conference on; 10/2009
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ABSTRACT: This paper describes the characterization and SPICE model adaptations for a SiGe Heterojunction Bipolar Transistor (HBT) with a characteristic emitter width of 0.4 mum, which is part of the device library in a commercial 0.35 mum SiGe BiCMOS technology. The developed model is used to design and validate the operation of an integrated driver for a 1550 nm Vertical Cavity Surface-Emitting Laser (VCSEL). The static measurements of the driver during irradiation up to 600 kGy correspond well with the simulations. A second irradiation experiment up to 1.6 MGy allowed us to verify the dynamic operation. Investigation of the eye diagram of the output signal both before and after irradiation revealed no significant signal degradation.
IEEE Transactions on Nuclear Science 09/2009; · 1.45 Impact Factor
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ABSTRACT: This paper describes the characterization and SPICE model adaptations for a SiGe Heterojunction Bipolar Transistor (HBT) with a characteristic emitter width of 0.4μm, which is part of the device library in a commercial 0.35μm SiGe BiCMOS technology. The developed model is used to design and validate the operation of an integrated driver for a 1550nm Vertical Cavity Surface-Emitting Laser (VCSEL). The static measurements of the driver during irradiation up to 600 kGy correspond well with the simulations. A second irradiation experiment up to 1.6 MGy allowed us to verify the dynamic operation. Investigation of the eye diagram of the output signal both before and after irradiation revealed no significant signal degradation.
Radiation and Its Effects on Components and Systems (RADECS), 2008 European Conference on; 10/2008
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ABSTRACT: The radiation hard design of a 155 Mb/s, 0.7 mum CMOS driver for a vertical-cavity surface-emitting laser (VCSEL) is presented. The circuit features enhanced tolerance to radiation induced shifts in the device characteristics by employing a replica-based feedback mechanism. The layout was achieved using an in-house developed radiation hardened component library. At a low dose rate of 4.5 Gy/h or 450 rad/h, the output current remains constant up to at least 3.5 kGy. At a dose rate of 21 kGy/h, the output current of the driver drops by 10% at a dose of 3.5 MGy and breaks down completely at 5.5 MGy.
IEEE Transactions on Nuclear Science 09/2007; · 1.45 Impact Factor
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ABSTRACT: A digital VCSEL driver has been designed, simulated and assessed under radiation, using discrete SiGe HBT's. The circuit tolerates high levels of gamma radiation, up to 12 MGy, features less than 2% drift in the forward current of the VCSEL and operates well above 10 MHz. The output duty cycle shows no notable degradation at 200 kHz, enabling the design of robust analog and digital communication systems using pulse-width-modulation (PWM) schemes.
Radiation and Its Effects on Components and Systems, 2005. RADECS 2005. 8th European Conference on; 10/2005
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ABSTRACT: Future maintenance tasks of the international experimental thermonuclear fusion reactor (ITER) will require communication links between the remotely operated equipment in the reactor vessel and the control room, that are radiation tolerant up to MGy dose levels. We therefore assessed the DC behaviour of a COTS SiGe heterojunction bipolar transistor (HBT) under gamma radiation up to more than 4 MGy. The DC current gain (beta) presents a limited loss of about 30% for a base current of 100 muA. Our in-situ measurements allowed us to adapt the manufacturer's SPICE model and account for these radiation effects. Circuit-hardened driving electronics for both photonic transmitters and receivers can hence be designed.
Radiation and Its Effects on Components and Systems, 2005. RADECS 2005. 8th European Conference on; 10/2005
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ABSTRACT: The paper compares two types of ESD-protection suited for the protection of CMOS low-noise amplifiers. This comparison is illustrated by the design and measurement of two high performance LNA prototypes. The first amplifier, with diode protection, targets the GPS L1 band at 1.57 GHz. It features a very low noise figure of 1.3 dB and a gain of 16.5 dB. The second amplifier was designed for 5 GHz wireless LAN applications and uses inductive ESD-protection. This prototype has a power gain of 20 dB and a noise figure of 3.5 dB. Both amplifiers surpass the industrial 2 kV HBM specification.
Microelectronic Test Structures, 2005. ICMTS 2005. Proceedings of the 2005 International Conference on; 05/2005
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ABSTRACT: This paper describes an approach to design ESD protection for integrated low noise amplifier (LNA) circuits used in narrowband transceiver front-ends. The RF constraints on the implementation of ESD protection devices are relaxed by co-designing the RF and the ESD blocks, considering them as one single circuit to optimise. The method is applied for the design of 0.25 μm CMOS LNA. Circuit protection levels higher than 3 kV HBM stress are achieved using conventional highly capacitive ggNMOS snapback devices. The methodology can be extended to other RF-CMOS circuits requiring ESD protection by merging the ESD devices in the functionality of the corresponding matching blocks.
Microelectronics Reliability. 01/2005;
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ABSTRACT: This work presents a 5 GHz LNA with on-chip ESD-protection provided by an integrated inductor. The circuit is implemented in a standard 0.18 μm CMOS technology. The LNA is matched at both input and output. It achieves a power gain of 20 dB with a noise figure of 3.5 dB at a power consumption of only 15 mW including the output buffer. The protection level complies with the class II HBM standard of 2 kV.
Solid-State Circuits Conference, 2004. ESSCIRC 2004. Proceeding of the 30th European; 10/2004
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ABSTRACT: Two optical front-ends implemented in a standard 0.18 μm CMOS technology are presented. They differ mainly in layout topology of the photodiode. The front-end with classical n-well diode achieves a bitrate of 300 Mbit/s. At an input power of -8 dBm, the BER is 2×10<sup>-10</sup>. The front-end with differential n-well diode outperforms the classical n-well topology and reaches bitrates up to 500 Mbit/s. At this speed, an input power of -8 dBm is sufficient to have a BER of 3×10<sup>-10</sup>. Both front-ends consume only 17 mW.
Solid-State Circuits Conference, 2004. ESSCIRC 2004. Proceeding of the 30th European; 10/2004
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ABSTRACT: This paper describes an approach to design ESD protection for integrated Low Noise Amplifier (LNA) circuits, used in narrowband transceiver front-ends. The RF constraints on the ESD devices are relaxed by co-designing the RF and the ESD blocks, considering them as one single circuit to optimize. The method is applied to the design of 0.25 mum CMOS LNA. Circuit protection levels higher than 3 kV HBM stress are achieved using conventional high capacitive ggNMOS snapback devices.
Electrical Overstress/Electrostatic Discharge Symposium, 2003. EOS/ESD '03.; 10/2003
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ABSTRACT: A study of the performance of photodiodes in a fully standard sub 0.1 μm technology is presented. A one-dimensional model is developed to get a rough idea of speed and responsivity of the detectors. Next, two-dimensional simulations of two basic unit cells are performed The importance of the side-wall capacitance of a junction is demonstrated, and a clear trade-off between speed and responsivity is shown. According to simulations, the nwell diode can achieve a bitrate of 200 Mbit/s and a responsivity of 0.36 A/W. By considering also the p<sup>+</sup> to nwell junction, a bitrate of 1 Gbit/s and a responsivity of 0.08 A/W can be achieved. Finally, the layout issues of different test diodes are discussed.
European Solid-State Device Research, 2003 33rd Conference on. ESSDERC '03; 10/2003
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ABSTRACT: This paper describes an optimization technique able to optimize a complete wireless receiver architecture in a reasonable amount of time. The optimizer alternates between SPICE level optimizations of simple building blocks and a full architecture optimization of the whole based on accurate models of the building blocks. The models of the building blocks are interpolated over the data points acquired in the SPICE level simulations. The optimizer technique has been applied to the optimization of an architecture for a GPS receiver. The optimal design has been implemented in a standard 0.25 μm CMOS process.
Computer Aided Design, 2002. ICCAD 2002. IEEE/ACM International Conference on; 12/2002
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ABSTRACT: This paper presents an ESD-protected 0.25 µm CMOS Low Noise Amplifier (LNA) for the Global Positioning System (GPS) operating at 1.57GHz. The performance specifications of high-end GPS receivers are quite severe, requiring designs with good sensitivity as well as LNAs with low noise figure and high gain. The LNA in this work features a 1.3dB noise figure and a power gain of 16.5dB. The input ESD-protection is more than 3kV Human Body Model (HBM) and the power consumption is only 9mW.
Solid-State Circuits Conference, 2002. ESSCIRC 2002. Proceedings of the 28th European; 10/2002
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ABSTRACT: In recent years, much research has been carried out on the
possibility of using pure CMOS, rather than bipolar or BiCMOS
technologies, for radio-frequency (RF) applications. An example of such
an application is the Global Positioning System (GPS). One of the
important bottlenecks to make the transition to pure CMOS is the
immunity of the circuits against electrostatic discharge (ESD). This
paper shows that it is possible to design a low-noise amplifier (LNA)
with very good RF performance and sufficient ESD immunity by carefully
co-designing both the LNA and ESD protection. This is demonstrated with
a 0.8-dB noise figure LNA with an ESD protection of -1.4-0.6 kV human
body model (HBM) with a power consumption of 9 mW. The circuit was
designed as a standalone LNA for a 1.2276-GHz GPS receiver. It is
implemented in a standard 0.25-μm 4M1P CMOS process
IEEE Journal of Solid-State Circuits 07/2002; · 3.23 Impact Factor
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ABSTRACT: A 0.25 μm CMOS quadrature complex bandpass low-IF GPS receiver
includes an LNA, PLL, mixer and a continuous-time ΔΣ ADC.
The chip has -130 dBm input sensitivity, 62 dB DR, and -32 dB IMRR,
while consuming 40 mW from 2 V supply. The chip is 9
mm<sup>2</sup>
Solid-State Circuits Conference, 2002. Digest of Technical Papers. ISSCC. 2002 IEEE International; 02/2002
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ABSTRACT: A new ESD protection methodology for high-frequency CMOS LNAs is
introduced. An on-chip inductor is employed to drain off the hazardous
ESD charge while tuning out the harmful parasitic input capacitance. A
5.2 GHz LNA has been designed, attaining high RF performance while
providing a high level of ESD protection
Electronics Letters 04/2001; · 0.96 Impact Factor
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ABSTRACT: The GPS L2 band, centered at 1.2276 GHz, is planned to enhance the
capabilities of civil GPS to backup the conventional GPS L1 link. As the
L2 receiver is required to detect a low power signal, an LNA with
extremely low noise figure is required. In addition, the LNA must
exhibit a large gain to suppress noise from the subsequent stages. This
ESD-protected CMOS LNA meets these requirements
Solid-State Circuits Conference, 2001. Digest of Technical Papers. ISSCC. 2001 IEEE International; 02/2001
