K. Muhammad

Texas Instruments Inc., Dallas, Texas, United States

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Publications (65)39.86 Total impact

  • [Show abstract] [Hide abstract]
    ABSTRACT: We present an adaptive predistortion system for a WLAN transceiver in 55nm CMOS. The forward DSP path utilizes complex gain predistortion while the APD module in the feedback path computes AMAM and AMPM coefficients by comparing ideal transmit signal with the distorted signal from the receiver. This module operates with various calibration signals generated on-chip in addition to TX data. Measurement results show improvement of EVM by 1dB with the proposed approach. Improvement of P1dB of more than 3dB was obtained using fully automatic processing. The total solution utilizes 120k gates.
    Custom Integrated Circuits Conference (CICC), 2013 IEEE; 01/2013
  • Chih-Ming Hung, Khurram Muhammad
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    ABSTRACT: With the ever-increasing functionalities of cellular smart phones and other communication systems, RF circuits at multi-GHz frequencies have recently migrated to the state-of-the-art low-cost digital CMOS processes despite their unfriendly analog design environment. The use of digital techniques to assist RF performance is becoming a common practice. However, there is a general fear that a fully integrated RF SoC containing DSPs could easily fail due to mysterious integration issues such as silicon substrate coupling. In this paper, we will visit some of the practical aspects based on the experiences of integrating the Digital RF Processor (DRP™) in the past ten years. Some conventional wisdom that is actually not wise for RF SoCs will be illustrated. As a result of the successful commercialization of DRPs, CMOS integrated radio SoCs with digitally assisted RF is proven to be one of the clever directions and has opened additional avenues toward software-defined radios.
    International Symposium on VLSI Technology, Systems, and Applications, Proceedings 01/2010;
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    ABSTRACT: This paper proposes and describes a new software and application programming interface view of an RF transceiver. It demonstrates benefits of using highly programmable digital control logic in an RF wireless system realized in a digital nanoscale CMOS process technology. It also describes a microprocessor architecture design in Digital RF Processor (DRP<sup>TM</sup>) and how it controls calibration and compensation for process, temperature and voltage variations of the analog and RF circuits to meet the required RF performance. A few calibration examples to reduce a DCO bias current and improve device reliability, as well as to optimize transmit modulation and receive performance, are given. The presented circuits and techniques have enabled successful implementation of a commercial single-chip GSM radio in 90 nm CMOS.
    IEEE Journal of Solid-State Circuits 01/2010; 45:276-288. · 3.06 Impact Factor
  • Meng-Chang Lee, Khurram Muhammad, Chih-Ming Hung
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    ABSTRACT: Discrete-time signal processing receivers combine gain, down-conversion, anti-aliasing, down-sampling, filtering and dc-offset compensation in one analog block to reduce the size of the solution. This paper presents an analog front-end (AFE) of a single-chip GSM/GPRS/EDGE (GGE) radio in 90nm digital CMOS which based on discrete-time analog signal processing. At the heart of the AFE is the passive switched-capacitor stages providing gain-boosting by impedance transformation while providing a 3<sup>rd</sup> order RC filter response. The AFE achieves 1.8dB NF with −19dBm IIP3. The filter occupies 0.2mm^2 and consumes only 7mA.
    VLSI Circuits, 2009 Symposium on; 07/2009
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    ABSTRACT: Migrating solutions to the most advance CMOS process node addresses cost reduction but increases RF interference within a SoC. In this paper we address the issue of design verification of single-chip RF SOCs in the presence of unintentional cross-couplings and leakages due to proximity of aggressors and victims. We will extend a previously presented VHDL based simulation methodology that accepts RF input and analyzes receiver BER performance, transmitter output distortion and phase noise by processing several thousand packets of baseband information while compensation algorithms are simultaneously executed. This approach allows building complex RF SoC systems based on behavioral models and has been successfully applied to investigate system behavior in the presence of aggressing nodes that create parasitic control loops due to unintentional and undesirable coupling paths.
    Radio Frequency Integrated Circuits Symposium, 2009. RFIC 2009. IEEE; 07/2009
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    ABSTRACT: In this paper we present a quad-band single-chip GSM/GPRS radio in 90 nm digital CMOS process based on the digital RF Processor (DRPtrade) technology. This chip integrates all functions from physical layer to the protocol stack and peripheral support in a single chip RF SoC. The transmitter uses a low-area small-signal digital polar architecture merging amplitude and phase information directly in an RF DAC. The receiver is based on direct RF sampling and discrete-time analog signal processing. A dedicated internal microprocessor manages the digital RF controls to provide best achievable RF performances. The transceiver exceeds all 3GPP specifications demonstrating a receive NF of 1.8 dB and a margin of 8 dB on TX spectral mask at 400 KHz offset in GSM850/900 bands. The transceiver is best-in-class in area and occupies only 3.8 mm<sup>2</sup> of silicon area.
    Radio Frequency Integrated Circuits Symposium, 2009. RFIC 2009. IEEE; 07/2009
  • I. Elahi, K. Muhammad, P.T. Balsara
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    ABSTRACT: We present a low-area implementation of an I/Q mismatch compensation (IQMC) circuit that comprises a correction engine and an adaptation engine. The correction engine performs I/Q mismatch compensation in the data path using a filter whose coefficients are updated after a programmable amount of time by a parallel adaptation engine that performs sample-by-sample off-line adaptation. This scheme allows very fast online adaptation while protecting the receiver data path from the degradations caused by a fast converging algorithm. The proposed scheme has been successfully implemented in 90-nm digital CMOS process for a low-IF quad-band GSM transceiver SoC. A single multiplier is used to perform complex multiplications for both correction and adaptation engines, resulting in a 0.025 mm<sup>2</sup> circuit. Image Rejection Ratio in excess of 50 dB is measured that is sufficient for IF frequencies as high as 200 kHz for GSM application.
    Circuits and Systems II: Express Briefs, IEEE Transactions on 02/2009; · 1.33 Impact Factor
  • Hunsoo Choo, Khurram Muhammad, Meng-Chang Lee
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    ABSTRACT: We present an active cancellation technique for removing the LO leakage signal at the input of the LNA in order to improve the IP2. The proposed method is implemented in a 65nm GSM/EDGE single chip radio and dramatically improves the IIP2 of the receiver by cancelling the static RF leakage at the input of the RF amplifiers.
    01/2009;
  • Imtinan Elahi, Khurram Muhammad
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    ABSTRACT: We present a low-complexity digital baseband detector for GSM applications for functional RF BIST of the receiver section of a complex transceiver SoC implemented in 90-nm digital CMOS process. The detector can be used as a pass/fail criterion during factory testing using a Tx-Rx RF loopback mode or with an inexpensive signal generator. It can also be used for testing of the analog and digital base-band data paths of the receiver without requiring any external equipment. The detector is implemented as part of a quad-band GSM/GPRS transceiver SoC implemented in 90-nm digital CMOS process and it occupies 0.05 mm2. In a special configuration of the receiver, the detector also supports a fully functional Bluetooth mode.
    01/2009;
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    ABSTRACT: The RF transceiver is built on the Digital RF Processor (DRP) technology. The ADPLL-based transmitter uses a polar architecture with all-digital PM-FM and AM paths. The receiver uses a discrete-time architecture in which the RF signal is directly sampled and processed using analog and DSP techniques. A 26 MHz digitally controlled crystal oscillator (DCXO) generates frequency reference (FREF) and has a means of high-frequency dithering to minimize the effects of coupling from digitally controlled PA driver (DPA) to DCXO by de-sensitizing its slicing buffer.
    Solid-State Circuits Conference, 2008. ISSCC 2008. Digest of Technical Papers. IEEE International; 03/2008
  • I. Elahi, K. Muhammad
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    ABSTRACT: A major contributor to degraded input-referred second-order intercept point (IIP2) in integrated RF systems-on-chips is local oscillator (LO) leakage to the input of RF circuits. In this brief, we present a digital calibration technique for improving IIP2 by injecting controlled dc offset at the mixer output through a three-port network of switched-capacitor filters. The dc offset at mixer output gets up-converted to LO frequency at the input of RF circuits due to poor reverse isolation of the receiver front-end. By controlling the amplitude of the injected dc, IIP2 degradation due to LO leakage at the input of RF amplifiers can be compensated. Mathematical analysis is presented and supported by measurement data from a quad-band GSM/GPRS receiver implemented in 90-nm digital CMOS process. Calibrated IIP2 of 50 dBm is reported for the receiver at low-noise amplifier input.
    Circuits and Systems II: Express Briefs, IEEE Transactions on 01/2008; · 1.33 Impact Factor
  • I. Elahi, K. Muhammad
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    ABSTRACT: We present a digital calibration technique for improving IIP2 by injecting DC offset at the mixer. Most receivers offer DC offset cancellation circuitry, and a targeted non-zero DC offset at mixer output is up-converted to RF carrier frequency due to poor reverse isolation of the mixer switch. By controlling amplitude of the injected DC, IIP2 degradation due to LO leakage at the input of RF amplifiers can be compensated. Mathematical analysis and measurement data for a quad-band GSM/GPRS receiver implemented in 90-nm digital CMOS process are presented. Calibrated IIP2 of 50 dBm is reported at LNA input.
    Custom Integrated Circuits Conference, 2007. CICC '07. IEEE; 10/2007
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    ABSTRACT: RF circuits for wireless applications have recently migrated to low-cost digital nanoscale CMOS processes, which are optimized for digital logic and SRAM memory, but are unfriendly for conventional analog and RF designs. We present fundamental techniques, recently developed for wireless RF transceivers, that transform the RF and analog circuit design complexities into the digital domain, where it may benefit from the process node scaling and the design automation environment. The all-digital phase locked loop, the all-digital control of phase and amplitude of a polar transmitter, and the direct RF sampling techniques in the receiver allow great flexibility in reconfigurable radio design. The ideas presented have been realized in several commercial digital RF processors offered by Texas Instruments, including single-chip Bluetooth and GSM radios.
    Radio Frequency Integrated Circuits (RFIC) Symposium, 2007 IEEE; 07/2007
  • Source
    K. Muhammad, T. Murphy, R.B. Staszewski
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    ABSTRACT: Single-chip RF SoCs are seeing widespread acceptance in wireless applications. In this paper we address the issue of design verification of single-chip RF SOCs in a framework that accepts RF input and analyzes receiver BER performance and transmitter output distortion and phase noise by processing several thousand packets of baseband information while compensation algorithms are simultaneously executed. No comprehensive methodology exists to date for designing such complex systems. This paper present a novel approach that allows building complex RF SoC systems based on VHDL modeling and simulation and opens up major avenues of model development for RF and analog circuits. This approach has been successfully applied to verify two generations of digital RF processors (DRP) in deep-submicron technologies
    IEEE Journal of Solid-State Circuits 06/2007; · 3.06 Impact Factor
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    Yongtao Wang, Khurram Muhammad, Kaushik Roy
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    ABSTRACT: This paper addresses the design of sigma-delta modulators with arbitrary signal and noise transfer functions using a genetic algorithm (GA)-based search method. The objective function is defined to include the difference D between the magnitude of the frequency responses of the designed transfer functions and the ideal one, the quantizer gain lambda<sub>critical</sub> for which the poles of the modulator start moving out of the unit circle, and the spread of the coefficients S. Stability can be improved by reducing lambda<sub>critical</sub> while a smaller S reduces the implementation complexity. A GA searches for poles/zeros of the transfer functions to minimize the objective function D+w<sub>1</sub>*lambda<sub>critical</sub>+w<sub>2</sub>*S, where w<sub>1</sub> and w<sub>2</sub> are two weighing factors. Numerical results demonstrate the effectiveness of the proposed method
    IEEE Transactions on Signal Processing 03/2007; · 2.81 Impact Factor
  • Chan Fernando, Khurram Muhammad
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    ABSTRACT: We present an efficient approach for evaluating the performance of a wireless receiver in the presence of calibration and/or compensation algorithms and various sources of measurement error. Noise figure and linearity performance of a receiver can be easily predicted over process and temperature variation and statistical estimates can be obtained to predict yield.
    01/2007;
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    ABSTRACT: This paper proposes and describes a new software and application programming interface view of an RF transceiver as implemented in the first single-chip GSM radio in 90 nm CMOS. It demonstrates benefits of using programmable digital control logic in deep-submicron CMOS RF system. It also describes a micro-processor architecture design in digital RF processor (DRP) and how it controls compensation for process, temperature and voltage variations of the analog and RF circuits to meet the required RF performance
    Custom Integrated Circuits Conference, 2006. CICC '06. IEEE; 10/2006
  • R.B. Staszewski, K. Muhammad, D. Leipold
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    ABSTRACT: Having gained experience in developing the first ever all-digital transmitter and digitally-intensive receiver for mobile phones in 90-nm CMOS, the authors offering in this paper are view into the future of highly integrated RF circuits. First experimental designs in 45-nm CMOS reveal highly unfriendly environment for analog and RF circuits design. The radio architecture to be successful must further transform the conventional voltage domain into high-speed and high-precision operation of predominantly digital circuitry
    Custom Integrated Circuits Conference, 2006. CICC '06. IEEE; 10/2006
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    R.B. Staszewski, K. Muhammad, D. Leipold
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    ABSTRACT: RF circuits for multi-GHz frequencies have recently migrated to low-cost digital deep-submicron CMOS processes. Unfortunately, this process environment, which is optimized only for digital logic and SRAM memory, is extremely unfriendly for conventional analog and RF designs. We present fundamental techniques recently developed that transform the RF and analog circuit design complexity to digital domain for a wireless RF transceiver, so that it enjoys the benefits of digital approach, such as process node scaling and design automation. All-digital phase locked loop, all-digital control of phase and amplitude of a polar transmitter, and direct RF sampling techniques allow great flexibility in reconfigurable radio design. Digital signal processing concepts are used to help relieve analog design complexity, allowing one to reduce cost and power consumption in a reconfigurable design environment. VHDL hardware description language is universally used throughout this SoC. The ideas presented have been used in Texas Instruments to develop two generations of commercial digital RF processors: a single-chip Bluetooth radio and a single-chip GSM radio
    Custom Integrated Circuits Conference, 2006. CICC '06. IEEE; 10/2006
  • I. Elahi, K. Muhammad, P.T. Balsara
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    ABSTRACT: Device mismatch in a mixer is generally believed to be the major contributor of second-order distortion that limits the performance of a direct conversion receiver. In this brief, we show that even with perfect matching, leakage at local oscillator frequency prior to mixing creates large second-order distortion when the third-order input intercept point of the receiver is not sufficiently large. Measurement data from a quad-band global system for mobile communications/global packet radio service transceiver implemented in 90-nm digital CMOS process is also presented to support our claim
    Circuits and Systems II: Express Briefs, IEEE Transactions on 09/2006; · 1.33 Impact Factor