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L. Mathew,
M. Sadd,
S. Kalpat,
M. Zavala,
T. Stephens,
R. Mora,
S. Bagchi,
C. Parker,
J. Vasek, D. Sing, [......],
G. Ablen,
Z. Shi,
J. Saenz,
B. Min,
D. Burnett,
B.-Y. Nguyen,
J. Mogab,
M.M. Chowdhury,
W. Zhang,
J.G. Fossum
[show abstract]
[hide abstract]
ABSTRACT: In this paper we demonstrate for the first time a novel CMOS IT-FET (inverted T channel FET) architecture. We demonstrate well functional ITFET SRAM bit-cells. Vertical devices such as FinFET and planar ultra thin body devices have been shown to exhibit good short channel control and proposed for future device scaling. The ITFET is novel device architecture that takes advantage of both vertical and horizontal thin-body devices. A doped channel IT-FET process has been developed and is the focus of this paper. This technology can be scaled beyond 45nm technologies using undoped channels. An ITFET device comprises of an ultra thin body planar horizontal channels and vertical channels in a single device. The devices have multi-gate control around these channels to improve short channel control. A single device has multiple orientations and hence mobility enhancement of both (110) and (100) planes can be used optimally. The devices presented have 15nm planar horizontal thin body and 40nm vertical channels of 100nm height, 17Aring gate dielectric and 50nm gate length. These devices are especially useful in circuits that need ratioing such as in SRAM cells and a well functional SRAM cell is demonstrated
Electron Devices Meeting, 2005. IEDM Technical Digest. IEEE International; 01/2006
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L. Mathew,
Yang Du,
S. Kaipat,
M. Sadd,
M. Zavala,
T. Stephens,
R. Mora,
R. Rai,
S. Becker,
C. Parker, [......],
L. Prabhu,
M. Moosa,
B.Y. Nguyen,
J. Mogah,
G.O. Workman,
A. Vandooren,
Z. Shi,
M.M. Chowdhury,
W. Zhang,
J.G. Fossum
[show abstract]
[hide abstract]
ABSTRACT: MIGFET devices have multiple gates to independently control the channel region. This allows for new device architectures and applications. This paper deals with three novel aspects discussed the first time I) Multi-fin MIGFET device with two independent gates capable of high current drives has been fabricated and demonstrated as a RF Mixer II) For the first time a MOSFET with three independent gates has been fabricated. These devices can be used in single transistor memories III) MIGFET has been used to characterize temperature effects on double gate devices in single electrode and independent gate modes. The three aspects discussed in the paper will have significant impact on future applications of these devices. The MIGFET can be integrated with double gate devices enabling novel analog circuits to scale with multi-gated digital CMOS in future digital CMOS transceiver (Single Chip Radio). The third independent gate in the MIGFET-T device enables novel memory architectures. Temperature characterization reveals the double gate Vt can be shifted both by temperature and by the second gate bias. This data enables compact modeling of temperature effects on independent gate devices to evaluate circuits that take advantage of this characteristic of the MIGFET.
VLSI Technology, 2005. Digest of Technical Papers. 2005 Symposium on; 07/2005
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L. Mathew,
Y. Du,
A.V.-Y. Thean,
M. Sadd,
A. Vandooren,
C. Parker,
T. Stephens,
R. Mora,
R. Rai,
M. Zavala, [......],
S. Kalpat,
J. Hughes,
R. Shimer,
S. Jallepalli,
G. Workman,
W. Zhang,
J.G. Fossum,
B.E. White,
B.-Y. Nguyen,
J. Mogab
[show abstract]
[hide abstract]
ABSTRACT: Perfectly self aligned vertical multiple independent gate field effect transistor (MIGFET) CMOS devices have been fabricated. The unique process used to fabricate these devices allow them to be integrated with FinFET devices. Device and circuit simulations have been used to explain the device and explore new applications using this device. A novel application of the MIGFET as a signal mixer has been demonstrated. The undoped channel, very thin body, perfectly matched gates allows charge coupling of the two signals and provide a new family of applications using the MIGFET mixer. Since the process allows integration of regular CMOS double gate devices and MIGFET devices this technology has potential for various digital and analog mixed-signal applications.
SOI Conference, 2004. Proceedings. 2004 IEEE International; 11/2004
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L. Mathew,
Yang Du,
A.V.-Y. Thean,
M. Sadd,
A. Vandooren,
C. Parker,
T. Stephens,
R. Mora,
Raghav Rai,
M. Zavala, D. Sing,
S. Kalpai,
J. Hughes,
R. Shimer,
S. Jallepalli,
G. Workman,
B.E. White,
B.-Y. Nguyen,
A. Mogab
[show abstract]
[hide abstract]
ABSTRACT: Device architectures incorporating multiple gate structures have been proposed to allow transistor scaling beyond the planar MCSFET integrations. These device architectures can improve performance such as better short channel performance and reduced leakage. In addition the additional channel surface and gate electrodes offers new circuit possibilities such as dynamic threshold voltage control and an RF mixer are demonstrated. It is desirable to fabricate multi-gated devices with the single gate on multiple sides and multiple gate electrodes this has been demonstrated successfully.
Integrated Circuit Design and Technology, 2004. ICICDT '04. International Conference on; 02/2004
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[show abstract]
[hide abstract]
ABSTRACT: It was shown recently that co-implantation of fluorine with boron
limits boron transient enhanced diffusion. This effect was shown to be a
chemical species effect by eliminating extraneous damage effects through
the use of pre-amorphized silicon. However, the nature of the fluorine
interaction with boron remained in question. In order to answer this
question, a series of experiments have been performed. Amorphization of
a n-type Czochralski wafer was achieved with a 70 keV Si<sup>+</sup>
implantation at a dose of 1×10<sup>15</sup>/cm<sup>2</sup>. The Si
<sup>+</sup> implant produced a 1400Å deep amorphous layer, which
was then implanted with a 1×10<sup>15</sup>/cm<sup>2</sup> B<sup>+
</sup> dose at an energy of either 1.1 keV or 500 eV. The samples were
then implanted with a dose of 2×10<sup>15</sup>/cm<sup>2</sup> F
<sup>+</sup> at various energies ranging from 2 keV to 36 keV. By
varying the F<sup>+</sup> energy it was possible to change the position
and concentration of the fluorine relative to the boron and the
end-of-range interstitial source. After annealing at 550°C, 750°
C, and 1050°C the wafers were analyzed by secondary ion mass
spectrometry (SIMS), transmission electron microscopy (TEM). Fluorine
co-implantation with boron causes the diffusion of boron to exhibit two
stages of diffusion during time frame that the control sample exhibits
transient enhanced diffusion. The results from this experiment and
supporting experiments suggest the fluorine is reducing the TED of the
boron by trapping silicon interstitials
Junction Technology, 2001. IWJT. Extended Abstracts of the Second International Workshop on; 02/2001
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L. Mathew,
M. Sadd,
B.E. White,
A. Vandooren,
S. Dakshina-Murthy,
J. Cobb,
T. Stephens,
R. Mora,
D. Pham,
J. Conner, [......],
Z. Shi,
A.V.-Y. Thean,
A. Barr,
M. Zavala,
J. Schaeffer,
M.J. Rendon, D. Sing,
M. Orlowski,
B.-Y. Nguyen,
J. Mogab
[show abstract]
[hide abstract]
ABSTRACT: A vertical double gate MOSFET structure with a new gate stack architecture has been demonstrated. The gate stack consists of two isolated polysilicon regions that are doped N+ and P+ with a metal/polysilicon strap connecting the doped regions. The device has an undoped channel yet performs as an enhancement mode MOSFET due to the asymetric doping of the gate regions on either side of the channel. The advantages of this structure include: 1) reduction of the Vt variations caused by dopant fluctuation in the channel region; 2) enhanced mobility due to an undoped channel region; 3) flexibility to adjust Vt across a wide range from depletion mode to very high Vt depending on the application; 4) lower interconnect resistance due to the use of metal/polysilicon gate components; 5) better manufacturability due to easier patterning of gate over spacer. The devices are enhancement mode with Vt ∼=(0.1-0.3V) at 100 nm gate length and channel thickness of less than 30 nm gate length and height 100 nm tall have been demonstrated. Functional devices at the 100 nm gate have Ion=191 μA/μm, Vt=0.3 V Ioff =0.5 μA/μm, SS=94 mV/decade. A different device with different implant dose and drive demonstrated Vt=0.15 V and SS=80mV/decade at Lgate=0.25 μm.
SOI Conference, 2003. IEEE International;
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L. Mathew,
M. Sadd,
S. Kalpat,
M. Zavala,
T. Stephens,
R. Mora,
R. Rai,
C. Parker,
J. Vasek, D. Sing, [......],
G. Ablen,
Z. Shi,
J. Saenz,
B. Min,
D. Burnett,
B.Y. Nguyen,
J. Mogab,
M.M. Chowdhury,
W. Zhang,
J.G. Fossum
[show abstract]
[hide abstract]
ABSTRACT: The ITFET is novel device architecture; it offers significant advantages over planar and FinFET technologies. The ITFET uses traditional CMOS processing technologies and can be rapidly inserted into existing SOI process flows. Doped channel ITFET devices have been demonstrated future work will include undoped channel ITFET devices. Simulated performances of the ITFET devices predict these devices can meet the 45nm and 32nm device performance. This transistor architecture offers device, process and application advantages
Integrated Circuit Design and Technology, 2006. ICICDT '06. 2006 IEEE International Conference on;
