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ABSTRACT: Detailed measurements of front- and back-channel characteristics in advanced SOI MOSFETs (ultrathin Si film, high-kappa, metal gate, and selective epitaxy of source/drain) are used to reveal and compare the transport properties at the corresponding Si/high- kappa (HfO<sub>2</sub> or HfSiON) and Si/SiO<sub>2</sub> interfaces. Low-temperature operation magnifies the difference between these two interfaces in terms of carrier mobility, threshold voltage, and subthreshold swing. As compared with Si/SiO<sub>2</sub>, the low-field mobility is lower at the Si/high-kappa interface and increases less rapidly at low temperature, reflecting additional scattering mechanisms governed by high-kappa and neutral defects.
IEEE Electron Device Letters 11/2009; · 2.85 Impact Factor
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ABSTRACT: Detailed measurements of front and back channel characteristics in advanced SOI MOSFETs (ultrathin film, metal gate, selective epitaxy of source/drain) are used to reveal the transport properties at the corresponding Si/high-K (HfO<sub>2</sub>/HfSiON) and Si/SiO<sub>2</sub> interfaces. Low-temperature operation magnifies the difference between these two interfaces in terms of carrier mobility, threshold voltage and subthreshold swing. As compared to Si/SiO<sub>2</sub>, the mobility is lower at the Si/high-K interface and increases less rapidly at low temperature, reflecting additional scattering mechanisms governed by high-K and neutral defects.
SOI Conference, 2008. SOI. IEEE International; 11/2008
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C. Fenouillet-Beranger,
S. Denorme,
B. Icard,
F. Boeuf,
J. Coignus,
O. Faynot,
L. Brevard,
C. Buj,
C. Soonekindt,
J. Todeschini, [......],
D. Galpin,
D. Pop,
R. Delsol,
R. Pantel,
F. Pionnier,
G. Thomas,
D. Bensahel,
S. Deleombus,
T. Skotnicki,
H. Mmgam
[show abstract]
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ABSTRACT: In this paper, we report on FD-SOI with high-k and single metal gate as a possible candidate for the 32 nm LOP and LSTP nodes. Good I<sub>on</sub>/I<sub>off</sub> performance for nMOS and pMOS transistors in the ultra-low-leakage regime (I<sub>off</sub>=6.6 pA/μm) are presented. In addition co-integration of high voltage devices with EOT 29A/V<sub>dd</sub> 1.8 V are made. For the first time, the functionality of 0.248 μm and 0.179 μm<sup>2</sup> 6T-SRAM bit-cells is demonstrated on FDSOI technology with a high-k/metal gate stack.
Electron Devices Meeting, 2007. IEDM 2007. IEEE International; 01/2008
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D. Aime,
C. Fenouillet-Beranger,
P. Perreau,
S. Denorme,
J. Coignus,
A. Cros,
D. Fleury,
O. Faynot, A. Vandooren,
R. Gassilloud, [......],
A. Zauner,
M. Muller,
V. Cosnier,
S. Minoref,
D. Bensahel,
M. Orlowski,
H. Mingam,
A. Wild,
S. Deleonibus,
T. Skotnicki
[show abstract]
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ABSTRACT: This paper describes the fabrication and electrical behavior of a fully-depleted SOI technology using a direct metal gate and high-k dielectric integrated on 300 mm SOI wafers for low power applications. We report ultra-thin FDSOI MOS transistors with WN metal gate (capped with TiN) on HfSiON gate dielectric. Performance at both device and circuit level are demonstrated and compared with TiN midgap metal gate.
Solid State Device Research Conference, 2007. ESSDERC 2007. 37th European; 10/2007
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F. Andrieu,
O. Faynot,
X. Garros,
D. Lafond,
C. Buj-Dufournet,
L. Tosti,
S. Minoret,
V. Vidal,
J.C. Barbe,
F. Allain, [......],
B. Guillaumot,
J.P. Colonna,
P. Besson,
L. Brevard,
D. Mariolle,
P. Holliger, A. Vandooren,
C. Fenouillet-Beranger,
F. Martin,
S. Deleonibus
[show abstract]
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ABSTRACT: This paper compares, for the first time, the scalability of physical- and chemical-vapor-deposited (PVD and CVD) TiN on HfO<sub>2 </sub> as a gate stack for FDSOI cMOSFETs down to 25nm gate length and width. It is shown that not only the intrinsic material properties but also the device architecture strongly influences the final gate stack properties. Reliability issues, stress and gate control in the sub-35nm scale are reported and explained, thanks to material, electric data and mechanical simulations. In spite of its lower performance on large device dimensions, PVD-TiN demonstrates a better overall trade-off, leading to a 17% ion improvement on 25nm short and narrow devices
Electron Devices Meeting, 2006. IEDM '06. International; 01/2007
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C. Gallon,
C. Fenouillet-Beranger, A. Vandooren,
F. Boeuf,
S. Monfray,
F. Payet,
S. Orain,
V. Fiori,
F. Salvetti,
N. Loubet, [......],
D. Delille,
F. Judong,
C. Perrot,
M. Hopstaken,
P. Scheblin,
P. Rivallin,
L. Brevard,
O. Faynot,
S. Cristoloveanu,
T. Skotnicki
[show abstract]
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ABSTRACT: The fully depleted (FD) SOI MOSFET is generally considered as one of the best candidates for next CMOS technology nodes. However, new technological boosters need to be introduced in the classical FD SOI process flow to reach the very aggressive I<sub>on</sub>/I<sub>off</sub> specifications predicted by the ITRS roadmap. The use of a thin buried oxide (BOX) on FD SOI is still a controversial subject, despite recent publications that have demonstrated its interest for improvement of short channel effect (SCE) control, especially with a ground plane (GP) integration (Tsuchiya et al.). In order to improve the device performances, a strained "contact etch stop layer" (CESL) technique has been successfully demonstrated to induce strain into the channel of bulk devices (Thompson et al., 2002) as well as in ultra-thin FD SOI devices (Singh et al., 2005 and Gallon et al., 2006). However, its compatibility with the specific technological features of FD SOI devices, such as silicon film thickness (T<sub>S1</sub>) variations, BOX material and BOX thickness (T<sub>BOX</sub>), raised source/drain architecture, has yet to be clarified. In this paper, we demonstrate, by electrical and mechanical simulations, the interest of thin BOX with GP, combined with a strained liner. These simulations have then been validated by measurements, showing excellent I<sub>on</sub>/I<sub>off</sub> pMOS performances
International SOI Conference, 2006 IEEE; 11/2006
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A. Vandooren,
C. Hobbs,
O. Faynot,
P. Perreau,
S. Denorme,
C. Fenouillet-Beranger,
C. Gallon,
C. Morin,
A. Zauner,
G. lmbert, [......],
Y. Le Tiec,
N. Gierczynski,
S Smith,
C. Laviron,
M. Bidaud,
I. Pouilloux,
D. Bensahel,
T. Skotnicki,
H. Mingam,
A Wild
[show abstract]
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ABSTRACT: A low power 45nm fully-depleted SOI technology is demonstrated for the first time on 300mm SOI wafers, using direct metal gate on high k dielectric and selective silicon epitaxy. Short p-channel devices exhibit very good performance. SRAM bit cells are fully functional down to 0.525μm<sup>2</sup> with good SNM and low leakage.
SOI Conference, 2005. Proceedings. 2005 IEEE International; 11/2005
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F. Andrieu,
T. Ernst,
O. Faynot,
Y. Bogumilowicz,
J.-M. Hartmann,
J. Eymery,
D. Lafond,
Y.-M. Levaillant,
C. Dupre,
R. Powers,
F. Fournel,
C. Fenouillet-Beranger, A. Vandooren,
B. Ghyselen,
C. Mazure,
N. Kernevez,
G. Ghibaudo,
S. Deleonibus
[show abstract]
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ABSTRACT: We report an original dual channel fully depleted CMOSFET architecture on insulator (DCOI) co-integrating strained-Si (nMOS) and strained-Si<sub>0.6</sub>Ge<sub>0.4</sub> (pMOS) with HfO<sub>2</sub>/TiN gate stacks down to 15nm gate length. We demonstrate for the first time an I<sub>ON</sub> improvement for short channel SOI of 10% at 35nm gate length (25% at 75nm, 100% on long channels) for both n- and p-MOSFETs and a more than 3 decades gate leakage reduction compared to a SiO<sub>2</sub> dielectric. Meanwhile, thanks to the dual channel engineering, a threshold voltage adjustment is performed with a mid gap single metal gate suitable for high performance (HP) CMOS.
SOI Conference, 2005. Proceedings. 2005 IEEE International; 11/2005
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ABSTRACT: We have performed measurements on double-gate Fin-FETs with independent gate contacts in order to study the coupling effects. In these devices, it is possible to separate the coupling between the two lateral channels and the coupling between one lateral channel and the back gate. The lateral coupling effect between the two gates is strong and can be used to tune the threshold voltage of the device whereas the vertical coupling is weaker and depends on the MIGFET size.
SOI Conference, 2005. Proceedings. 2005 IEEE International; 11/2005
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L. Mathew,
Yang Du,
S. Kaipat,
M. Sadd,
M. Zavala,
T. Stephens,
R. Mora,
R. Rai,
S. Becker,
C. Parker, [......],
L. Prabhu,
M. Moosa,
B.Y. Nguyen,
J. Mogah,
G.O. Workman, A. Vandooren,
Z. Shi,
M.M. Chowdhury,
W. Zhang,
J.G. Fossum
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ABSTRACT: MIGFET devices have multiple gates to independently control the channel region. This allows for new device architectures and applications. This paper deals with three novel aspects discussed the first time I) Multi-fin MIGFET device with two independent gates capable of high current drives has been fabricated and demonstrated as a RF Mixer II) For the first time a MOSFET with three independent gates has been fabricated. These devices can be used in single transistor memories III) MIGFET has been used to characterize temperature effects on double gate devices in single electrode and independent gate modes. The three aspects discussed in the paper will have significant impact on future applications of these devices. The MIGFET can be integrated with double gate devices enabling novel analog circuits to scale with multi-gated digital CMOS in future digital CMOS transceiver (Single Chip Radio). The third independent gate in the MIGFET-T device enables novel memory architectures. Temperature characterization reveals the double gate Vt can be shifted both by temperature and by the second gate bias. This data enables compact modeling of temperature effects on independent gate devices to evaluate circuits that take advantage of this characteristic of the MIGFET.
VLSI Technology, 2005. Digest of Technical Papers. 2005 Symposium on; 07/2005
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S. Monfray,
D. Chanemougame,
S. Borel,
A. Talbot,
F. Leverd,
N. Planes,
D. Delille,
D. Dutartre,
R. Palla,
Y. Morand,
S. Descombes,
M.-P. Samson,
N. Vulliet,
T. Sparks, A. Vandooren,
T. Skotnicki
[show abstract]
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ABSTRACT: In this paper, we demonstrate for the first time full integration of highly performant NMOS and PMOS silicon-on-nothing (SON) devices into circuits. We demonstrated fully functional SRAMs cells with very good yield, showing static noise margin (SNM) of 175mV and write margin (WM, stable "read 0") above 500mV. The optimized SON devices show performance for NMOS and for PMOS that is among the best published data (with drive current up to 1100/350μA/μm for 138/20nA/μm I<sub>off</sub> for NMOS and PMOS devices respectively @V<sub>dd</sub>=1.2V, I<sub>ox</sub>=16A). Finally, we present also the implementation of the SON process into a new "localized SOI" architecture on bulk. This new and simplified SON process is also demonstrated by fully operational SRAM cells.
Electron Devices Meeting, 2004. IEDM Technical Digest. IEEE International; 01/2005
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L. Mathew,
Y. Du,
A.V.-Y. Thean,
M. Sadd, A. Vandooren,
C. Parker,
T. Stephens,
R. Mora,
R. Rai,
M. Zavala, [......],
S. Kalpat,
J. Hughes,
R. Shimer,
S. Jallepalli,
G. Workman,
W. Zhang,
J.G. Fossum,
B.E. White,
B.-Y. Nguyen,
J. Mogab
[show abstract]
[hide abstract]
ABSTRACT: Perfectly self aligned vertical multiple independent gate field effect transistor (MIGFET) CMOS devices have been fabricated. The unique process used to fabricate these devices allow them to be integrated with FinFET devices. Device and circuit simulations have been used to explain the device and explore new applications using this device. A novel application of the MIGFET as a signal mixer has been demonstrated. The undoped channel, very thin body, perfectly matched gates allows charge coupling of the two signals and provide a new family of applications using the MIGFET mixer. Since the process allows integration of regular CMOS double gate devices and MIGFET devices this technology has potential for various digital and analog mixed-signal applications.
SOI Conference, 2004. Proceedings. 2004 IEEE International; 11/2004
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C. Gallon,
C. Fenouillet-Beranger,
Y.M. Meziani,
J.P. Cesso,
J. Lusakowski,
F. Teppe,
N. Dyakonova, A. Vandooren,
W. Knap,
G. Ghibaudo,
D. Delille,
S. Cristoloveanu,
T. Skotnicki
[show abstract]
[hide abstract]
ABSTRACT: We propose to compare the main classical methods used for mobility parameters extraction (static method or split C-V) with a new approach based on magnetoresistance (MR) measurements. We focus on short channel devices behavior and compare it with long channel transistor behavior. This exhaustive study indicates that the magnetoresistance method is well adapted for thin film mobility extraction for fully-depleted SOI devices as thin as 10 nm.
SOI Conference, 2004. Proceedings. 2004 IEEE International; 11/2004
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A.V.-Y. Thean, A. Vandooren,
S. Kalpat,
Y. Du,
I. To,
J. Hughes,
T. Stephens,
B. Goolsby,
T. White,
A. Barr, [......],
M. Rossow,
D. Roan,
D. Pham,
R. Rai,
S. Murphy,
B.-Y. Nguyen,
B.E. White,
A. Duvallet,
T. Dao,
J. Mogab
[show abstract]
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ABSTRACT: In this paper, we report the performance and reliability of sub-100nm TaSiN metal gate fully depleted SOI devices with high-k gate dielectric. Performance differences between fully-depleted and partially-depleted devices are highlighted. This is also the first time that an unique asymmetric degradation phenomenon between electron and hole mobility in metal/high-k devices is reported. Despite the use of high-k dielectric, we show that these devices exhibit superior reliability, noise and analog circuit performances.
VLSI Technology, 2004. Digest of Technical Papers. 2004 Symposium on; 07/2004
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L. Mathew,
Yang Du,
A.V.-Y. Thean,
M. Sadd, A. Vandooren,
C. Parker,
T. Stephens,
R. Mora,
Raghav Rai,
M. Zavala,
D. Sing,
S. Kalpai,
J. Hughes,
R. Shimer,
S. Jallepalli,
G. Workman,
B.E. White,
B.-Y. Nguyen,
A. Mogab
[show abstract]
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ABSTRACT: Device architectures incorporating multiple gate structures have been proposed to allow transistor scaling beyond the planar MCSFET integrations. These device architectures can improve performance such as better short channel performance and reduced leakage. In addition the additional channel surface and gate electrodes offers new circuit possibilities such as dynamic threshold voltage control and an RF mixer are demonstrated. It is desirable to fabricate multi-gated devices with the single gate on multiple sides and multiple gate electrodes this has been demonstrated successfully.
Integrated Circuit Design and Technology, 2004. ICICDT '04. International Conference on; 02/2004
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Bich-Yen Nguyen,
A. Thean,
T. White, A. Vandooren,
M. Sadaka,
L. Mathew,
A. Barr,
S. Thomas,
M. Zalava,
Da Zhang, [......],
S. Kalpat,
L. Prabhu,
V. Kaushik,
Y. Du,
T. Dao,
M. Mendicino,
M. Orlowski,
P. Tobin,
J. Mogab,
S. Venkatesan
[show abstract]
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ABSTRACT: In this paper, we will detail the issues with new materials being introduced into CMOS devices and present some potential solutions to enable high performance and low power CMOS for the 65nm node and beyond.
Integrated Circuit Design and Technology, 2004. ICICDT '04. International Conference on; 02/2004
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A. Vandooren,
A.V.Y. Thean,
Y. Du,
I. To,
J. Hughes,
T. Stephens,
M. Huang,
S. Egley,
M. Zavala,
K. Sphabmixay, [......],
M. Rossow,
D. Roan,
D. Pham,
R. Rai,
B.-Y. Nguyen,
B. White,
M. Orlowski,
A. Duvallet,
T. Dao,
J. Mogab
[show abstract]
[hide abstract]
ABSTRACT: We report for the first time, the digital and analog performance of sub-100nm Fully-Depleted Silicon-On-Insulator (SOI) n and p-MOSFETs using TaSiN gate and HfO<sub>2</sub> dielectric with elevated Source/Drain (SD) extensions. As CMOS technology continues to scale down, the FDSOI technology offers a potential solution to control short channel effects by reducing the silicon film thickness and a concurrent scaling of the buried oxide thickness. The use of metal gate and thin undoped body offer the additional advantages of 1) suppression of polysilicon depletion effects, 2) elimination of boron penetration, 3) minimizing S/D junction capacitance (Cj), and 4) enhancing transistor matching performance for mixed signal application. High k dielectric is necessary to reduce gate leakage for EOT below 15 to 20Å. The intrinsic low-leakage nature of the FDSOI device and it's immunity to floating body effect provides much opportunity for ultra-low power digital and analog applications. Physical and electrical analyses of the devices are presented to provide an assessment of the metal gates on high K gate dielectric in combination with fully-depleted device operation in the context of digital and analog circuits.
Electron Devices Meeting, 2003. IEDM '03 Technical Digest. IEEE International; 01/2004
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A. Vandooren,
S. Egley,
M. Zavala,
T. Stephens,
L. Mathew,
M. Rossow,
A. Thean,
A. Barr,
Z. Shi,
T. White,
D. Pham,
J. Conner,
L. Prabhu,
D. Triyoso,
J. Schaeffer,
D. Roan,
Bich-Yen Nguyen,
M. Orlowski,
J. Mogab
[show abstract]
[hide abstract]
ABSTRACT: In this paper, we demonstrate for the first time CMOS thin-film metal gate FDSOI devices using HfO<sub>2</sub> gate dielectric at the 50-nm physical gate length. Symmetric V<sub>T</sub> is achieved for long-channel nMOS and pMOS devices using midgap TiN single metal gate with undoped channel and high-k dielectric. The devices show excellent performance with a I<sub>on</sub>=500 μA/μm and I<sub>off</sub>=10 nA/μm at V<sub>DD</sub>=1.2 V for nMOSFET and I<sub>on</sub>=212 μA/μm and I<sub>off</sub>=44 pA/μm at V<sub>DD</sub>=-1.2 V for pMOSFET, with a CET=30 Å and a gate length of 50 nm. DIBL and SS values as low as 70 mV/V nand 77 mV/dec, respectively, are obtained with a silicon film thickness of 14 nm. Ring oscillators with 15 ps stage delay at V<sub>DD</sub>=1.2 V are also realized.
IEEE Transactions on Nanotechnology 01/2004; · 2.29 Impact Factor
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[show abstract]
[hide abstract]
ABSTRACT: Experimental results for low and high temperature operation are presented on advanced FDSOI transistors with mid-gap metal gated thin film and high-k dielectric. The temperature dependence of the threshold voltage, subthreshold swing, transconductance and electron mobility is used to analyze the quality of Si film/high-k interface as well as transport mechanisms.
European Solid-State Device Research, 2003 33rd Conference on. ESSDERC '03; 10/2003
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A. Vandooren,
A. Barr,
L. Mathew,
T.R. White,
S. Egley,
D. Pham,
M. Zavala,
S. Samavedam,
J. Schaeffer,
J. Conner,
B.-Y. Nguyen,
B.E. White Jr,
M.K. Orlowski,
J. Mogab
[show abstract]
[hide abstract]
ABSTRACT: We report for the first time the performance of ultrathin film fully-depleted (FD) silicon-on-insulator (SOI) CMOS transistors using HfO/sub 2/ gate dielectric and TaSiN gate material. The transistors feature 100-150 /spl Aring/ silicon film thickness and selective epitaxial silicon growth in the source/drain extension regions. TaSiN-gate shows good threshold voltage control using an undoped channel, which reduces threshold voltage variation with silicon film thickness and discrete, random dopant placement. Device processing for CMOS fabrication is drastically simplified by the use of the same gate material for both n- and p-MOSFETs. Electrical characterization results illustrate the combined impact of using high-k dielectric and metal gate on the performance of ultrathin film FD SOI devices.
IEEE Electron Device Letters 06/2003; · 2.85 Impact Factor
