N. Subba

Advanced Micro Devices, Sunnyvale, California, United States

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Publications (17)11.46 Total impact

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    ABSTRACT: Critical currents (I<sub>CRIT</sub>) extracted from the N-curves of a 6-T SRAM bit cell have been shown in recent research to be important and effective figures of merit for the cell¿s stability and write-ability. SPICE models of cell transistors, therefore, not only need to fit closely to individual transistor¿s I-V characteristics, but also faithfully reproduce I<sub>CRIT</sub>s¿ behavior of the cell as a whole. A branch current analysis is performed to reveal individual transistors¿ impact on I<sub>CRIT</sub>s¿ and their key bias regions. Based on the insight from the analysis, an efficient SPICE model extraction flow is proposed that enables decoupled fine tuning of the pass-gate, pull-down, and pull-up transistor models to achieve satisfactory fit to I<sub>CRIT</sub>s without model extraction iterations.
    Solid-State and Integrated-Circuit Technology, 2008. ICSICT 2008. 9th International Conference on; 11/2008
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    ABSTRACT: Accurate extraction of the SPICE model parameter is critical in the CMOS IC design. However, it faces difficult issues in state-of-the-art MOSFET technology. First, the gate CV parameter extraction is challenging due to small values and many extrinsic components that need to be de-embedded. Second, the systematic offset of the gate critical dimension (CD) exists between test structures and circuits, introducing a significant uncertainty. Thus, it is not uncommon that the validation of a circuit-level SPICE model involves arbitrary adjustments of capacitance parameters that undermine the confidence level of the model parameters. This paper presents seamless methodologies to resolve these issues. Circuit-level validation of the methodology is given for 65nm PD-SOI ring oscillators (ROs), covering a wide range of simulation conditions.
    01/2008;
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    ABSTRACT: Speculative SPICE models (also referred to as evaluation-level or guess models), which are extracted based on projected device electrical characteristics (called `targets¿) rather than actual measurement data, are required to support concurrent IC designs. The self-heating effect in silicon-on-insulator (SOI) technologies presents additional challenges in obtaining quality speculative SOI MOSFET models. A novel `shift-and-ratio¿ technique is developed to generate self-heating free device targets from raw targets provided only at room temperature, and a corresponding speculative model extraction methodology is proposed. The shift-and-ratio technique is validated by using silicon data of 65 nm partially-depleted (PD) SOI technologies. The adequacy and self-consistency of the speculative model extraction methodology is demonstrated in field testing where a large number of 65 nm and 45 nm PD SOI speculative models are extracted. Availability of self-heating free targets proves to be critical not only for improved speculative model extraction efficiency, but also for model quality in general by ensuring physical and reasonable temperature dependences in the resulting speculative models.
    01/2008;
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    ABSTRACT: Logic performance is improved by creating more stress in the channel in advanced CMOS technologies. Impact of stress on different circuit blocks in a microprocessor chip has not been studied in detail. This paper presents a comprehensive study on the effects of stress and the corresponding process steps on various circuit characteristics. Analog behavior, hysteresis and noise properties are investigated to understand the effect of stress on them. These characteristics play important roles in determining the performances of analog/phy, I/O and PLL blocks respectively. It is shown that the type of process steps used for stress optimization can significantly alter the performance of various circuits.
    37th European Solid State Device Research Conference, 2007. ESSDERC; 10/2007
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    ABSTRACT: A new methodology is proposed to extract self-heating free I-V curves, including the substrate current, of SOI MOSFETs based on triple-temperature, regular DC measurement. It is verified to be accurate with Hspice simulations and suitable for SPICE model parameter extraction. It is also demonstrated that extraction of self-heating free I-V curves is not only desired for efficient SPICE model generation, but also required to accurately capture the true temperature dependences in the models.
    Microelectronic Test Structures, 2007. ICMTS '07. IEEE International Conference on; 04/2007
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    ABSTRACT: This paper presents a new integrated silicon-on-insulator (SOI) substrate-diode (SUBD) structure for an electrostatic-discharge (ESD) protection of the SOI I/O circuits. The diode is built under the buried oxide, within the substrate region of the SOI wafer, without additional steps to the conventional SOI CMOS process. This paper shows that the ESD protection level can reach four times the level of the standard SOI lateral-diode structure. This paper presents the device and process simulation results to demonstrate the effect of self-heating in both the standard SOI lateral and substrate diodes, and to demonstrate how to optimize the SUBD structure using a deep n-well implant
    IEEE Transactions on Device and Materials Reliability 07/2006; · 1.52 Impact Factor
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    ABSTRACT: Transport in Si NMOSFETs with gate lengths from 48 to 23 nm is investigated by full-band Monte Carlo device simulation for three sets of devices: (I) unstrained Si control devices, (II) process matched strained Si devices, and (III) threshold voltage matched strained Si devices. While the process matched strained Si devices show the same performance improvement for all gate lengths, this is not the case for the threshold voltage matched devices for which the performance improvement degrades with shrinking gate length due to the heavier doping.
    Solid-State Electronics 08/2004; · 1.48 Impact Factor
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    ABSTRACT: With the introduction of ultra-thin (<15Å) gate dielectrics, which have significantly higher nitrogen concentration, and thus a higher dielectric constant, many new reliability challenges need to be addressed. At the same time, high-performance transistors are now migrating from bulk to silicon-on-insulator (SOI) to boost the performance. This paper will discuss major reliability issues such as negative bias temperature instability (NBTI), hot carrier injection (HCI), time dependent dielectric breakdown (TDDB) and electro-static discharge stress (ESD), etc., facing the state of art technology for SOI.
    Solid-State Electronics 01/2004; · 1.48 Impact Factor
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    ABSTRACT: A feasibility study of domino circuits using partially depleted SOI technology is conducted by focusing on the OR structure, known to be particularly sensitive to current leakage. By contrast to previous belief, the simulation results indicated that for the 0.145 μm technology node, the circuit could be destabilized by the floating body effects enhanced (channel) off current rather than parasitic BJT current. It was observed that current spiking also played a major role in discharging the pre-charge node during operation. It was found that this overall leakage (discharging) limited the number of input transistors on the OR circuit. It was therefore deemed necessary to make the level-restoring transistor stronger and/or limit the number of inputs to keep the circuit robust during operation. Keeping the body grounded was found to be an alternative solution to both of these leakage problems.
    Solid-State Electronics. 02/2003;
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    ABSTRACT: An experimental demonstration is given of the reduction of floating body effects in narrow channel SOI MOSFETs, as manifested by the saturation region subthreshold characteristics, latch-up, and breakdown voltage. The mechanisms responsible for this reduction are explained by original experiments and simulations. These are a deterioration of the carrier lifetime near the channel edges caused by local stress and defects, and a lowering of the source-body built-in potential barrier, resulting from dopant outdiffusion/segregation into the isolation oxide
    IEEE Electron Device Letters 02/2002; · 2.79 Impact Factor
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    ABSTRACT: Narrow-width effects are investigated in LOCOS and STI-isolated silicon-on-insulator (SOI) MOSFETs. With width as a parameter, variations in threshold voltage, mobility, subthreshold swing and drain-induced barrier lowering are analyzed in relationship with the other transistor dimensions (i.e. channel length, and film thickness). For both isolation techniques, a strong dependence of the threshold voltage with the channel width as well as the SOI silicon film thickness are observed while narrow and short-channel effects are not found to be correlated. Following this, it is shown through saturation subthreshold swing, latch-up and breakdown voltage measurements, that the floating-body effects (FBEs) are reduced in narrow-channel devices. Specific experiments (current transients, source–body junction current…) and simulations were conducted to reveal the mechanisms responsible for the observed weakening of the FBEs. It is concluded that three main mechanisms coexist: (i) the local thinning of the film under the LOCOS isolation, (ii) a lower carrier lifetime near the channel edges and (iii) an increase of the source/body junction leakage near the edges which speeds up the removal of the carriers from the body.
    Solid-State Electronics 01/2002; · 1.48 Impact Factor
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    ABSTRACT: We focus on the floating body effects (FBEs) in narrow channel SOI MOSFETs such as saturation subthreshold swing, breakdown voltage and single transistor latch-up. We find that all improve as the channel width decreases and examine the mechanisms causing this improvement. We demonstrate experimently and by simulation, that the reduced FBEs in narrow channel devices are caused by dopant outdiffusion and lifetime reduction along the channel edges
    SOI Conference, 2001 IEEE International; 02/2001
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    ABSTRACT: The ongoing need to increase the speed in tandem with decrease in power consumption has necessitated for an alternative viable technology. Due to device physics and structural properties (i.e., reduced junction capacitance, higher driving current etc) and limited technology transfer, Partially-Depleted (PD) SOI technology has become the de-facto candidate for replacing Bulk CMOS technology. It has matured to an extent that it can now be implemented in most of the applications. This paper explains how design parameters for pseudo n-MOS can be changed to maximize the advantage of SOI technology. Further, we extend this idea to dynamic logic circuits and evaluate its viability
    Semiconductor Device Research Symposium, 2001 International; 02/2001
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    ABSTRACT: The narrow-channel effects (NCE) and their impact on the floating body effects (FBEs) are investigated by various static and dynamic measurements in both LOCOS and STI isolated devices. It is found that FBEs are reduced in narrow channel devices for both isolation technologies. Two possible mechanisms are found to be consistent with our results: a carrier lifetime degradation on the sidewalls or an increase of the source/body junction leakage on the edges. Both mechanisms are discussed on the basis of our experimental results and on previous studies in bulk or SOI devices.
    Microelectronic Engineering 01/2001; 59:483-488. · 1.22 Impact Factor
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    ABSTRACT: Bulk pseudo-nMOS (i.e. CMOS with grounded pMOS pullup device) circuits have been quite popular in the past because they are fast, small and pMOS devices are good pullup resistive loads. A pseudo-nMOS gate with a fan-in of N requires only N+1 transistors (as opposed to 2N for standard CMOS), resulting in smaller area as well as smaller parasitic capacitances, whereas each input connects to only one transistor, presenting a smaller load to the preceding gate. Since these advantages come at the expense of static power consumption, pseudo-nMOS circuits have often lost their appeal for large circuits, even though they are frequently used in some critical path elements when speed and area are at a premium (Weste and Eshraghian, 1993). If a weaker pMOS load transistor could be used without sacrificing speed, for example by reducing the load on the dotted node (either due to smaller devices in the pulldown tree, or to a smaller driven load representing a similar gate), the static power could be minimized. Since from a circuit designer's perspective, one of the major advantages of SOI technology is the reduction of junction capacitance, this paper takes a fresh look at pseudo-nMOS and finds that SOI technology makes possible important performance (speed and power) and area improvements and predicts that it can be used widely in the design of SOI custom-integrated circuits
    SOI Conference, 2000 IEEE International; 02/2000
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    ABSTRACT: An empirical correlation model of I dlow , the MOSFET drain current measured at V gs =V dd /2 and V ds =V dd , where V dd is the supply voltage, is proposed based on the alpha-power law model. It enables a comprehensive analysis of I dlow over a wide range of device geometry, supply voltage, and temperature in multi-threshold-voltage technologies. Built upon and verified by electrical-test data of 90nm partially-depleted (PD) silicon-on-insulator (SOI) technologies, the newly developed methodology provides practical and efficient guidelines to device target projection and target-based speculative SPICE model extraction.
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    ABSTRACT: An a priori hysteresis modeling methodology in partially depleted (PD) silicon-on-insulator (SOI) technologies is proposed that constitutes an essential part of an improved compact model extraction flow. By focusing on the parasitic currents, the capacitance network, the body effect, and fine-tuning the diode characteristics especially, the proposed methodology aims to closely capture the voltage and temperature dependences of hysteresis well before the full-fledged MOSFET model extraction begins. The resulting benefits, such as improved model extraction efficiency, relatively high fidelity to hardware data, and improved model accuracy, are demonstrated on a state-of-the-art 90 nm PD SOI technology.

Publication Stats

61 Citations
11.46 Total Impact Points

Institutions

  • 2006–2008
    • Advanced Micro Devices
      Sunnyvale, California, United States
  • 2000–2003
    • George Mason University
      • Department of Electrical and Computer Engineering
      Fairfax, VA, United States
  • 2002
    • AMD
      Sunnyvale, California, United States