N. Subba

George Mason University, Fairfax, VA, United States

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Publications (8)5.5 Total impact

  • [show abstract] [hide abstract]
    ABSTRACT: With the introduction of ultra-thin (<15Å) gate dielectrics, which have significantly higher nitrogen concentration, and thus a higher dielectric constant, many new reliability challenges need to be addressed. At the same time, high-performance transistors are now migrating from bulk to silicon-on-insulator (SOI) to boost the performance. This paper will discuss major reliability issues such as negative bias temperature instability (NBTI), hot carrier injection (HCI), time dependent dielectric breakdown (TDDB) and electro-static discharge stress (ESD), etc., facing the state of art technology for SOI.
    Solid-State Electronics. 01/2004;
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    ABSTRACT: A feasibility study of domino circuits using partially depleted SOI technology is conducted by focusing on the OR structure, known to be particularly sensitive to current leakage. By contrast to previous belief, the simulation results indicated that for the 0.145 μm technology node, the circuit could be destabilized by the floating body effects enhanced (channel) off current rather than parasitic BJT current. It was observed that current spiking also played a major role in discharging the pre-charge node during operation. It was found that this overall leakage (discharging) limited the number of input transistors on the OR circuit. It was therefore deemed necessary to make the level-restoring transistor stronger and/or limit the number of inputs to keep the circuit robust during operation. Keeping the body grounded was found to be an alternative solution to both of these leakage problems.
    Solid-State Electronics. 02/2003;
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    ABSTRACT: An experimental demonstration is given of the reduction of floating body effects in narrow channel SOI MOSFETs, as manifested by the saturation region subthreshold characteristics, latch-up, and breakdown voltage. The mechanisms responsible for this reduction are explained by original experiments and simulations. These are a deterioration of the carrier lifetime near the channel edges caused by local stress and defects, and a lowering of the source-body built-in potential barrier, resulting from dopant outdiffusion/segregation into the isolation oxide
    IEEE Electron Device Letters 02/2002; · 2.79 Impact Factor
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    ABSTRACT: Narrow-width effects are investigated in LOCOS and STI-isolated silicon-on-insulator (SOI) MOSFETs. With width as a parameter, variations in threshold voltage, mobility, subthreshold swing and drain-induced barrier lowering are analyzed in relationship with the other transistor dimensions (i.e. channel length, and film thickness). For both isolation techniques, a strong dependence of the threshold voltage with the channel width as well as the SOI silicon film thickness are observed while narrow and short-channel effects are not found to be correlated. Following this, it is shown through saturation subthreshold swing, latch-up and breakdown voltage measurements, that the floating-body effects (FBEs) are reduced in narrow-channel devices. Specific experiments (current transients, source–body junction current…) and simulations were conducted to reveal the mechanisms responsible for the observed weakening of the FBEs. It is concluded that three main mechanisms coexist: (i) the local thinning of the film under the LOCOS isolation, (ii) a lower carrier lifetime near the channel edges and (iii) an increase of the source/body junction leakage near the edges which speeds up the removal of the carriers from the body.
    Solid-State Electronics 01/2002; · 1.48 Impact Factor
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    ABSTRACT: We focus on the floating body effects (FBEs) in narrow channel SOI MOSFETs such as saturation subthreshold swing, breakdown voltage and single transistor latch-up. We find that all improve as the channel width decreases and examine the mechanisms causing this improvement. We demonstrate experimently and by simulation, that the reduced FBEs in narrow channel devices are caused by dopant outdiffusion and lifetime reduction along the channel edges
    SOI Conference, 2001 IEEE International; 02/2001
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    ABSTRACT: The ongoing need to increase the speed in tandem with decrease in power consumption has necessitated for an alternative viable technology. Due to device physics and structural properties (i.e., reduced junction capacitance, higher driving current etc) and limited technology transfer, Partially-Depleted (PD) SOI technology has become the de-facto candidate for replacing Bulk CMOS technology. It has matured to an extent that it can now be implemented in most of the applications. This paper explains how design parameters for pseudo n-MOS can be changed to maximize the advantage of SOI technology. Further, we extend this idea to dynamic logic circuits and evaluate its viability
    Semiconductor Device Research Symposium, 2001 International; 02/2001
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    ABSTRACT: The narrow-channel effects (NCE) and their impact on the floating body effects (FBEs) are investigated by various static and dynamic measurements in both LOCOS and STI isolated devices. It is found that FBEs are reduced in narrow channel devices for both isolation technologies. Two possible mechanisms are found to be consistent with our results: a carrier lifetime degradation on the sidewalls or an increase of the source/body junction leakage on the edges. Both mechanisms are discussed on the basis of our experimental results and on previous studies in bulk or SOI devices.
    Microelectronic Engineering 01/2001; 59:483-488. · 1.22 Impact Factor
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    ABSTRACT: Bulk pseudo-nMOS (i.e. CMOS with grounded pMOS pullup device) circuits have been quite popular in the past because they are fast, small and pMOS devices are good pullup resistive loads. A pseudo-nMOS gate with a fan-in of N requires only N+1 transistors (as opposed to 2N for standard CMOS), resulting in smaller area as well as smaller parasitic capacitances, whereas each input connects to only one transistor, presenting a smaller load to the preceding gate. Since these advantages come at the expense of static power consumption, pseudo-nMOS circuits have often lost their appeal for large circuits, even though they are frequently used in some critical path elements when speed and area are at a premium (Weste and Eshraghian, 1993). If a weaker pMOS load transistor could be used without sacrificing speed, for example by reducing the load on the dotted node (either due to smaller devices in the pulldown tree, or to a smaller driven load representing a similar gate), the static power could be minimized. Since from a circuit designer's perspective, one of the major advantages of SOI technology is the reduction of junction capacitance, this paper takes a fresh look at pseudo-nMOS and finds that SOI technology makes possible important performance (speed and power) and area improvements and predicts that it can be used widely in the design of SOI custom-integrated circuits
    SOI Conference, 2000 IEEE International; 02/2000

Publication Stats

31 Citations
5.50 Total Impact Points


  • 2000–2003
    • George Mason University
      • Department of Electrical and Computer Engineering
      Fairfax, VA, United States
  • 2002
    • AMD
      Sunnyvale, California, United States