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ABSTRACT: In this paper, we propose using joint equalization and coding to improve on-chip communication speeds by signaling at rates beyond the rate governed by resistance-capacitance (RC) delay of the interconnect. Operating beyond the RC limit introduces inter-symbol interference (ISI). We mitigate the effects of ISI by employing equalization. The proposed equalizer employs a variable threshold inverter whose switching threshold is modified as a function of past output of the bus. We demonstrate even higher speedups by combining equalization with crosstalk avoidance coding. Specifically, simulation results for a 10-mm 32-bit bus in 0.13-mum CMOS technology show that 1.28 speedup is achievable by equalization alone and 2.30 speedup is achievable by joint equalization and coding.
IEEE Transactions on Very Large Scale Integration (VLSI) Systems 04/2008; · 1.22 Impact Factor
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ABSTRACT: A reliable high-speed bus employing low-swing signaling can be designed by encoding the bus to prevent crosstalk and provide error correction. Coding for on-chip buses requires additional bus wires and codec circuits. In this paper, fundamental bounds on the number of wires required to provide joint crosstalk avoidance and error correction using memoryless codes are presented. The authors propose a code construction that results in practical codec circuits with the number of wires being within 35% of the fundamental bounds. When applied to a 10-mm 32-bit bus in a 0.13-mum CMOS technology with low-swing signaling, one of the proposed codes provides 2.14times speedup and 27.5% energy savings at the cost of 2.1times area overhead, but without any loss in reliability
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems 06/2007; · 1.27 Impact Factor
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ABSTRACT: In this paper, we propose joint repeater insertion and crosstalk avoidance coding as a low-power alternative to repeater insertion for global bus design in nanometer technologies. We develop a methodology to calculate the repeater size and separation that minimize the total power dissipation for joint repeater insertion and coding for a specific delay target. This methodology is employed to obtain power vs. delay trade-offs for 130-nm, 90-nm, 65-nm, and 45-nm technology nodes. Using ITRS technology scaling data, we show that proposed technique provides 54%, 67%, and 69% power savings over optimally repeater-inserted 10-mm 32-bit bus at 90-nm, 65-nm, and 45-nm technology nodes, respectively, while achieving the same delay.
Low Power Electronics and Design, 2005. ISLPED '05. Proceedings of the 2005 International Symposium on; 09/2005
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ABSTRACT: Global buses in deep-submicron (DSM) system-on-chip designs consume significant amounts of power, have large propagation delays, and are susceptible to errors due to DSM noise. Coding schemes exist that tackle these problems individually. In this paper, we present a coding framework derived from a communication-theoretic view of a DSM bus to jointly address power, delay, and reliability. In this framework, the data is first passed through a nonlinear source coder that reduces self and coupling transition activity and imposes a constraint on the peak coupling transitions on the bus. Next, a linear error control coder adds redundancy to enable error detection and correction. The framework is employed to efficiently combine existing codes and to derive novel codes that span a wide range of tradeoffs between bus delay, codec latency, power, area, and reliability. Using simulation results in 0.13-/spl mu/m CMOS technology, we show that coding is a better alternative to repeater insertion for delay reduction as it reduces power dissipation at the same time. For a 10-mm 4-bit bus, we show that a bus employing the proposed codes achieves up to 2.17/spl times/ speed-up and 33% energy savings over a bus employing Hamming code. For a 10-mm 32-bit bus, we show that 1.7/spl times/ speed-up and 27% reduction in energy are achievable over an uncoded bus by employing low-swing signaling without any loss in reliability.
IEEE Transactions on Very Large Scale Integration (VLSI) Systems 07/2005; · 1.22 Impact Factor
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[show abstract]
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ABSTRACT: In this paper we propose using joint equalization and coding to improve on-chip communication speeds by signaling at rates beyond the rate governed by RC delay of the interconnect. Operating beyond the RC limit introduces intersymbol interference (ISI). We mitigate the effects of ISI by employing equalization. The proposed equalizer employs a variable threshold inverter whose switching threshold is modified as a function of past output of the bus. We demonstrate even higher speed-ups by combining equalization with crosstalk avoidance coding. Specifically, simulation results for a 10-mm 32-bit bus in 0.13-μm CMOS technology show that 1.28× speed-up is achievable by equalization alone and 2.30× speed-up is achievable by joint equalization and coding.
Quality of Electronic Design, 2005. ISQED 2005. Sixth International Symposium on; 04/2005
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ABSTRACT: A reliable high-speed bus employing low-swing signaling can be designed by encoding the bus to prevent crosstalk and provide error correction. In this paper, we present fundamental limits on the number of wires required to achieve joint crosstalk avoidance and error correction in on-chip buses. We propose a code construction that results in practical encoding and decoding schemes with the number of wires being within 35% of the fundamental limits. The proposed codes, when applied to a 10-mm 32-bit bus in a 0.13-μ CMOS technology with low-swing signaling, provide 2.14× speed-up and 27.5% energy savings without any loss in reliability.
VLSI Design, 2005. 18th International Conference on; 02/2005
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ABSTRACT: Capacitive crosstalk between adjacent wires in long on-chip buses significantly increases propagation delay in the deep submicron regime. A high-speed bus can be designed by eliminating crosstalk delay through bus encoding. In this paper, we present an overview of the existing coding schemes and show that they require either a large wiring overhead or complex encoder-decoder circuits. We propose a family of codes referred to as overlapping codes that reduce both overheads. We construct two codes from this family and demonstrate their superiority over existing schemes in terms of area and energy dissipation. Specifically, for a 1-cm 32-bit bus in 0.13-μm CMOS technology, we present a 48-wire solution that has 1.98× speed-up, 10% energy savings and requires 20% less area than shielding.
Computer Design: VLSI in Computers and Processors, 2004. ICCD 2004. Proceedings. IEEE International Conference on; 11/2004
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ABSTRACT: In this paper, we present a novel algorithmic noise-tolerance (ANT) technique referred to as reduced precision redundancy (RPR). RPR requires a reduced precision replica whose output can be employed as the corrected output in case the original system computes erroneously. When combined with voltage overscaling (VOS), the resulting soft digital signal processing system achieves up to 60% and 44% energy savings with no loss in the signal-to-noise ratio (SNR) for receive filtering in a QPSK system and the butterfly of fast Fourier transform (FFT) in a WLAN OFDM system, respectively. These energy savings are with respect to optimally scaled (i.e., the supply voltage equals the critical voltage V/sub dd-crit/) present day systems. Further, we show that the RPR technique is able to maintain the output SNR for error rates of up to 0.09/sample and 0.06/sample in an finite impulse response filter and a FFT block, respectively.
IEEE Transactions on Very Large Scale Integration (VLSI) Systems 06/2004; · 1.22 Impact Factor
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Design Automation Conference, 2004. Proceedings. 41st; 02/2004
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ABSTRACT: In this paper, we present a detailed analysis of the system design choices available for low-power high-speed I/O link transceivers. Using the transceiver power dissipation as the metric, we compare three equalization schemes (linear equalizer, decision-feedback equalizer, and transmit pre-emphasis) in combination with three pulse amplitude modulation (PAM) schemes (2-PAM, 4-PAM, and 8-PAM). The input signal levels and the filter lengths in the equalizer are chosen to minimize the power dissipation while meeting a bit error rate constraint. We show that, for a typical 20" intersymbol interference dominated link, transmit pre-emphasis in combination with 4-PAM results in 75 data rates.
Signals, Systems and Computers, 2003. Conference Record of the Thirty-Seventh Asilomar Conference on; 12/2003
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ABSTRACT: We propose a technique for designing low-power fast Fourier
transform (FFT) processors with applications in next generation wireless
LAN and wireless access systems. The proposed low-power technique is
based on the general principle of soft digital signal processing where
voltage overscaling (VOS) (scaling the supply voltage beyond the
critical voltage V<sub>dd-crit</sub> required for correct operation) is
applied in conjunction with algorithmic noise-tolerance (ANT)
techniques. We propose an ANT technique referred to as reduced precision
redundancy for compensating the degradation in the signal-to-noise ratio
(SNR) at an FFT output due to VOS. Simulation results using the proposed
scheme with 0.25 μm standard CMOS technology show that the power
consumption in a butterfly functional unit of an FFT processor can be
reduced by 44% over a conventional voltage-scaled system without any SNR
loss in the context of a typical orthogonal frequency division
multiplexing (OFDM) based WLAN system
Signal Processing Systems, 2001 IEEE Workshop on; 02/2001
