A. Schaefer

University of Technology Munich, München, Bavaria, Germany

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Publications (9)0 Total impact

  • Conference Proceeding: An x86-64 core implemented in 32nm SOI CMOS
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    ABSTRACT: The 32 nm implementation of an AMD x86-64 core occupying 9.69 mm<sup>2</sup> and containing more than 35 million transistors (excluding L2 cache), operates at frequencies >3 GHz. The core incorporates numerous design and power improvements to enable an operating range of 2.5 to 25 W and a zero-power gated state that make the core well-suited to a broad range of mobile and desktop products.
    Solid-State Circuits Conference Digest of Technical Papers (ISSCC), 2010 IEEE International; 03/2010
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    Conference Proceeding: A simulation model of HIV treatment under drug scarcity constraints
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    ABSTRACT: We consider a population of HIV infected patients. In resource poor environments, decision makers must allocate antiretro-viral drugs (ARVs) to patients in need of them the most. Further complicating matters is that once a patient is given ARVs, the decision maker must decide when to deny further access to ARVs. We compare various methods for determining which patients should receive ARVs and when to switch a patient off of ARVs. We examine the World Health Organization's (WHO) treatment recommendations and how the level of drug shortages can influence the performance of these recommendations. Instead of a single recommendation, the WHO offers three distinct treatment policies with no mention of when to use them. We find that the severity of drug shortages can greatly impact the performance of these policies and the performance gap can be as high as 1.4 years.
    Simulation Conference (WSC), Proceedings of the 2009 Winter; 01/2010
  • Conference Proceeding: Highly Scalable Signals in Space for Future High Data Rate Military Applications
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    ABSTRACT: Future military communications systems, on both national and international levels, will demand the capability of transmitting high data rates over self-organising ad-hoc networks. In the work presented in this paper we describe a high data rate signal in space (HDR-SiS) developed by Rohde & Schwarz, that enables the transmission of real time video, voice and data in a mobile ad-hoc network (MANET). The transmission scheme uses OFDM at bandwidths ranging from 1 MHz to 10 MHz in order to be adaptable to various national and international spectral usage requirements. OFDM has the advantage of a high spectral efficiency and, given an appropriate design, simple equalisation techniques can be used in order to deal with multi-path channel environments. Although OFDM is already used in many standards such as WLAN, WiMAX, DVB-T, these systems were designed for either stationary and/or indoor applications. The presented SiS is optimised for mobile operators with relative speeds up to several hundred kilometres per hour and multi-path delays corresponding to relative distances of around 15 km
    Military Communications Conference, 2006. MILCOM 2006. IEEE; 11/2006
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    Conference Proceeding: Incremental and decremental redundancy in turbo source-channel coding
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    ABSTRACT: For joint source channel coding we extend the concept of incremental redundancy to a combination of decremental and incremental redundancy in a parallel concatenated turbo scheme. Even for compression only the new scheme outperforms Lempel-Ziv compression, but has many advantages in adaptive type II FEC/ARQ systems for the transmission over noisy channels.
    Control, Communications and Signal Processing, 2004. First International Symposium on; 02/2004
  • Conference Proceeding: Analog decoders and receivers for high speed applications
    J. Hagenauer, M. Moerz, A. Schaefer
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    ABSTRACT: The ever increasing speed of data transmission, especially in optical channels, in magnetic recording devices and in wireless links, makes it necessary to look at new receiver structures which are capable of high speed processing at low power consumption. Analog, nonlinear and highly parallel operating circuits can perform the tasks of equalization, differential detection, channel decoding and, in some cases, of source decoding which are normally assigned to digital processors and circuits. The first prototype analog VLSI chips of simple decoder components are available and perform well at speeds up to 10 Gbit/s
    Broadband Communications, 2002. Access, Transmission, Networking. 2002 International Zurich Seminar on; 02/2002
  • Conference Proceeding: Analog decoding of high rate tailbiting codes using the dual trellis
    M. Moerz, A. Schaefer, E. Offer
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    ABSTRACT: A novel analog decoder design for high rate convolutional codes is presented. The decoder complexity is considerably reduced compared to conventional approaches in analog VLSI
    Information Theory, 2001. Proceedings. 2001 IEEE International Symposium on; 02/2001
  • Conference Proceeding: Analog decoders for high rate convolutional codes
    M. Moerz, A. Schaefer, E. Offer, J. Hagenauer
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    ABSTRACT: Recently, several VLSI implementations of analog decoders have been reported for rate 1/2 tailbiting convolutional codes. The main advantages of analog decoders are much higher decoding speed, smaller chip size and lower power consumption when compared to an equivalent digital decoder. Since many high speed applications require code rates well above 1/2 we focus on high rate tailbiting convolutional codes. For digital decoder implementations it has been shown by C. Weiss and J. Berkmann (see Proc. 3rd ITG Conf. Source and Channel Coding, Munich, Germany, p.199-207, Jan. 2000) that it is advantageous to use the trellis of the dual code which is less complex for high rate codes. The novel analog decoder design proposed in this paper can be seen as a direct analog implementation of the algorithm described by Weiss and Berkman
    Information Theory Workshop, 2001. Proceedings. 2001 IEEE; 02/2001
  • Conference Proceeding: An all-analog ring network for turbo-detection of convolutionally encoded DPSK signals
    J. Hagenauer, A. Schaefer, C. Weiss
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    ABSTRACT: The turbo-principle is more far reaching than the original turbo code concept. Encoded DPSK transmission, e.g., can be viewed as a serial concatenation of a channel code with a rate-one code representing the DPSK modulation. Iterative decoding of this concatenated scheme shows surprisingly good performance. We describe the serial concatenation of interleaved tail-biting convolutional codes (TBCC) with this DPSK rate-one code transmitted over AWGN and flat Rayleigh fading channels. The receiver performs time-continuous “turbo” iterations between the inner and outer codes and is realized by two analog ring networks connected via an interleaver ring which exchanges extrinsic information by means of analog signals being continuous in time and value
    Information Theory, 2000. Proceedings. IEEE International Symposium on; 02/2000
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    Conference Proceeding: Analog rotating ring decoder for an LDPC convolutional code
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    ABSTRACT: We present an analog rotating ring decoder for decoding an LDPC convolutional code. The decoder architecture uses a window of soft received L-values, K time units in the past and K time units in the future, to decode a given bit. The window of 2K+1 time units is arranged in a ring structure, and decoding proceeds in a continuous fashion by rotating around the ring. Simulation results indicate performance almost identical to that achieved with digital decoding.
    Information Theory Workshop, 2003. Proceedings. 2003 IEEE;