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ABSTRACT: A novel two-transistor (2T) floating-body cell (FBC) for embedded-DRAM applications is proposed and demonstrated via device/circuit simulations using a process/physics-based compact model, with numerical-simulation support. Significant advantages of the 2T cell, in which the charged/discharged body of one transistor (1T) drives the gate of the other, over the currently popular 1T-DRAM FBC are noted and explained. Furthermore, a modification of the basic 2T-FBC structure, which in essence results in a floating-body/gate cell (FBGC), is shown to yield dramatic reduction in power dissipation in addition to better signal margin, longer data retention, and higher memory density. Design and processing issues that need to be addressed for optimal performance and for sustained FBGC viability in nanoscale CMOS are discussed.
IEEE Transactions on Electron Devices 07/2008; · 2.32 Impact Factor
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ABSTRACT: In this paper we propose a novel two-transistor (2T) FBC for DRAM applications that can yield much better signal margin and density, while offering other significant advantages over the 1T cell. The key features of the 2T FBC are demonstrated via process/physics-based device/circuit simulations, supported by numerical results.
SOI Conference, 2007 IEEE International; 11/2007
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R. F. Steimle,
R. Muralidhar,
R. Rao, M. Sadd,
C. T. Swift,
J. Yater,
B. Hradsky,
S. Straub,
H. Gasquet,
L. Vishnubhotla,
E. J. Prinz,
T. Merchant,
B. Acred,
K. Chang,
B. E. White Jr
Microelectronics Reliability. 01/2007; 47:585-592.
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Non-Volatile Semiconductor Memory Workshop, 2006. IEEE NVSMW 2006. 21st; 02/2006
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Non-Volatile Semiconductor Memory Workshop, 2006. IEEE NVSMW 2006. 21st; 02/2006
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ABSTRACT: A two bit/cell embedded nanocrystal bitcell with low write current SSI program and tunnel erase in which nanocrystals are located under dedicated control gates has been demonstrated. Write bias conditions which mitigate gate disturb in a top erase capable bitcell have been confirmed
Non-Volatile Semiconductor Memory Workshop, 2006. IEEE NVSMW 2006. 21st; 02/2006
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L. Mathew, M. Sadd,
S. Kalpat,
M. Zavala,
T. Stephens,
R. Mora,
S. Bagchi,
C. Parker,
J. Vasek,
D. Sing, [......],
G. Ablen,
Z. Shi,
J. Saenz,
B. Min,
D. Burnett,
B.-Y. Nguyen,
J. Mogab,
M.M. Chowdhury,
W. Zhang,
J.G. Fossum
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ABSTRACT: In this paper we demonstrate for the first time a novel CMOS IT-FET (inverted T channel FET) architecture. We demonstrate well functional ITFET SRAM bit-cells. Vertical devices such as FinFET and planar ultra thin body devices have been shown to exhibit good short channel control and proposed for future device scaling. The ITFET is novel device architecture that takes advantage of both vertical and horizontal thin-body devices. A doped channel IT-FET process has been developed and is the focus of this paper. This technology can be scaled beyond 45nm technologies using undoped channels. An ITFET device comprises of an ultra thin body planar horizontal channels and vertical channels in a single device. The devices have multi-gate control around these channels to improve short channel control. A single device has multiple orientations and hence mobility enhancement of both (110) and (100) planes can be used optimally. The devices presented have 15nm planar horizontal thin body and 40nm vertical channels of 100nm height, 17Aring gate dielectric and 50nm gate length. These devices are especially useful in circuits that need ratioing such as in SRAM cells and a well functional SRAM cell is demonstrated
Electron Devices Meeting, 2005. IEDM Technical Digest. IEEE International; 01/2006
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L. Mathew,
Yang Du,
S. Kaipat, M. Sadd,
M. Zavala,
T. Stephens,
R. Mora,
R. Rai,
S. Becker,
C. Parker, [......],
L. Prabhu,
M. Moosa,
B.Y. Nguyen,
J. Mogah,
G.O. Workman,
A. Vandooren,
Z. Shi,
M.M. Chowdhury,
W. Zhang,
J.G. Fossum
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ABSTRACT: MIGFET devices have multiple gates to independently control the channel region. This allows for new device architectures and applications. This paper deals with three novel aspects discussed the first time I) Multi-fin MIGFET device with two independent gates capable of high current drives has been fabricated and demonstrated as a RF Mixer II) For the first time a MOSFET with three independent gates has been fabricated. These devices can be used in single transistor memories III) MIGFET has been used to characterize temperature effects on double gate devices in single electrode and independent gate modes. The three aspects discussed in the paper will have significant impact on future applications of these devices. The MIGFET can be integrated with double gate devices enabling novel analog circuits to scale with multi-gated digital CMOS in future digital CMOS transceiver (Single Chip Radio). The third independent gate in the MIGFET-T device enables novel memory architectures. Temperature characterization reveals the double gate Vt can be shifted both by temperature and by the second gate bias. This data enables compact modeling of temperature effects on independent gate devices to evaluate circuits that take advantage of this characteristic of the MIGFET.
VLSI Technology, 2005. Digest of Technical Papers. 2005 Symposium on; 07/2005
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B. Hradsky,
R. Muralidhar,
R.A. Rao,
B. Steimle,
S. Straub,
B.E. White Jr, M. Sadd,
S.G.H. Anderson,
J.A. Yater,
C.T. Swift,
B. Acred,
J. Peschke,
E.J. Prinz,
K.M. Chang
Device Research Conference Digest, 2005. DRC '05. 63rd; 02/2005
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L. Mathew,
Y. Du,
A.V.-Y. Thean, M. Sadd,
A. Vandooren,
C. Parker,
T. Stephens,
R. Mora,
R. Rai,
M. Zavala, [......],
S. Kalpat,
J. Hughes,
R. Shimer,
S. Jallepalli,
G. Workman,
W. Zhang,
J.G. Fossum,
B.E. White,
B.-Y. Nguyen,
J. Mogab
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ABSTRACT: Perfectly self aligned vertical multiple independent gate field effect transistor (MIGFET) CMOS devices have been fabricated. The unique process used to fabricate these devices allow them to be integrated with FinFET devices. Device and circuit simulations have been used to explain the device and explore new applications using this device. A novel application of the MIGFET as a signal mixer has been demonstrated. The undoped channel, very thin body, perfectly matched gates allows charge coupling of the two signals and provide a new family of applications using the MIGFET mixer. Since the process allows integration of regular CMOS double gate devices and MIGFET devices this technology has potential for various digital and analog mixed-signal applications.
SOI Conference, 2004. Proceedings. 2004 IEEE International; 11/2004
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R.F. Steimle,
R. Rao, M. Sadd,
C. Swift,
B. Hradsky,
S. Straub,
T. Merchant,
M. Stoker,
C. Parikh,
S. Anderson,
M. Rossow,
J. Yater,
B. Acred,
K. Harber,
E. Prinz,
B.E. White Jr,
R. Muralidhar
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ABSTRACT: Silicon nanocrystals provide opportunity to solve the challenging problem of tunnel oxide scaling of conventional flash memories by increasing immunity to charge loss via tunnel oxide defects. New aspects in silicon nanocrystal memory technology include Coulomb blockade or charge confinement effects, atomistic nucleation, and nanocrystal passivation to preserve them during subsequent processing and program/erase endurance characteristics. This paper discusses the above characteristics and culminates in presenting salient results from 4 Mb NOR memory arrays fabricated using 90 nm CMOS technology. Excellent memory characteristics including tight Vt distributions are obtained using a tunnel oxide thickness of 5 nm and a 6 V power supply.
Nanotechnology, 2004. 4th IEEE Conference on; 09/2004
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R. Muralidhar,
R.F. Steimle, M. Sadd,
R. Rao,
C.T. Swift,
E.J. Prinz,
J. Yater,
L. Grieve,
K. Harber,
B. Hradsky, [......],
W. Chen,
L. Parker,
S.G.H. Anderson,
M. Rossow,
T. Merchant,
M. Paransky,
T. Huynh,
D. Hadad,
Ko-Min Chang,
B.E. White Jr
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ABSTRACT: This paper reports on the first functional 6V, 4Mb silicon nanocrystal based nonvolatile memory array using conventional 90nm and 0.25μm process technologies. The silicon nanocrystal based NOR Flash can be programmed and erased using conventional techniques in floating gate memories. Key aspects of this technology are the ability to form nanocrystals of the right size and density, the ability to protect them from subsequent processing effects and the ability to remove them from undesired areas. The use of isolated silicon nanocrystals for charge storage provides the opportunity to reduce the program and erase voltages due to tunnel oxide scaling and also has potential for two bits/cell operation. Optimization of tunnel and control oxides is critical to obtain high program/erase cycling endurance. Due to the area savings from memory module peripheral voltage scaling and the reduction in mask count over conventional floating gate technology, silicon nanocrystal non-volatile memory technology can substantially reduce the cost of embedded flash at the 90nm technology node and beyond.
Integrated Circuit Design and Technology, 2004. ICICDT '04. International Conference on; 02/2004
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L. Mathew,
Yang Du,
A.V.-Y. Thean, M. Sadd,
A. Vandooren,
C. Parker,
T. Stephens,
R. Mora,
Raghav Rai,
M. Zavala,
D. Sing,
S. Kalpai,
J. Hughes,
R. Shimer,
S. Jallepalli,
G. Workman,
B.E. White,
B.-Y. Nguyen,
A. Mogab
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ABSTRACT: Device architectures incorporating multiple gate structures have been proposed to allow transistor scaling beyond the planar MCSFET integrations. These device architectures can improve performance such as better short channel performance and reduced leakage. In addition the additional channel surface and gate electrodes offers new circuit possibilities such as dynamic threshold voltage control and an RF mixer are demonstrated. It is desirable to fabricate multi-gated devices with the single gate on multiple sides and multiple gate electrodes this has been demonstrated successfully.
Integrated Circuit Design and Technology, 2004. ICICDT '04. International Conference on; 02/2004
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Bich-Yen Nguyen,
A. Thean,
T. White,
A. Vandooren,
M. Sadaka,
L. Mathew,
A. Barr,
S. Thomas,
M. Zalava,
Da Zhang, [......],
S. Kalpat,
L. Prabhu,
V. Kaushik,
Y. Du,
T. Dao,
M. Mendicino,
M. Orlowski,
P. Tobin,
J. Mogab,
S. Venkatesan
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ABSTRACT: In this paper, we will detail the issues with new materials being introduced into CMOS devices and present some potential solutions to enable high performance and low power CMOS for the 65nm node and beyond.
Integrated Circuit Design and Technology, 2004. ICICDT '04. International Conference on; 02/2004
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R. Muralidhar,
R.F. Steimle, M. Sadd,
R. Rao,
C.T. Swift,
E.J. Prinz,
J. Yater,
L. Grieve,
K. Harber,
B. Hradsky, [......],
W. Chen,
L. Parker,
S.G.H. Anderson,
M. Rossow,
T. Merchant,
M. Paransky,
T. Huynh,
D. Hadad,
Ko-Min Chang,
B.E. White Jr
[show abstract]
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ABSTRACT: The first functional 6 V, 4 Mb silicon nanocrystal based nonvolatile memory arrays using conventional 90 nm and 0.25 μm process technologies have been produced. The technology can be programmed and erased using conventional techniques in floating gate memories and can substantially reduce the cost of embedded flash at the 90 nm node and beyond.
Electron Devices Meeting, 2003. IEDM '03 Technical Digest. IEEE International; 01/2004
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ABSTRACT: This paper introduces a silicon nanocrystal-silicon nitride hybrid single transistor cell for potential dynamic RAM (DRAM) applications that stores charge in silicon nanocrystals or a silicon nitride charge trapping layer or both. The memory operates in the direct tunneling regime for the tunnel oxide and so presents the possibility of a DRAM with good cycling endurance. The silicon nanocrystals of this hybrid device present intermediate states that facilitate tunneling transport to and from the nitride layer. Short time measurements show that the hybrid silicon nanocrystal silicon nitride based DRAM cell programs and erases much faster than a plain SONOS implementation while offering better data retention, memory signal and longer refresh time than a silicon nanocrystal type DRAM.
IEEE Transactions on Nanotechnology 01/2004; · 2.29 Impact Factor
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ABSTRACT: We have performed two-dimensional (2-D) and three-dimensional (3-D) computer simulations of random dopant fluctuations in 25-nm planar n-channel metal-oxide-semiconductor field effect transistor (MOSFET) with superhalo channel doping. Our study shows that 2-D simulations that neglect lateral percolation of the carriers can overestimate the impact on threshold voltage (V<sub>T</sub>) fluctuations by as much as a factor of four. Fundamental differences in the way the 2-D and 3-D models describe subthreshold and near-threshold conduction are highlighted in our study. Our models reveal that surface percolation of carriers is an effective agent for reducing V<sub>T</sub> fluctuations. In addition, the halo only enhances the V<sub>T</sub> fluctuations by approximately 10%. Though the influence of the superhalo in the device may be overwhelmed by atomistic granularity according to the 2-D model, 3-D simulations show that the halo continues to function coherently for the MOSFET ensemble when charge percolation is accounted.
IEEE Transactions on Nanotechnology 07/2003; · 2.29 Impact Factor
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ABSTRACT: We have studied the oxidation of Si nanocrystals as a function of oxidizing ambient, temperature, time, and initial nanocrystal size using x-ray photoelectron spectroscopy, transmission electron microscopy, and energy-filtered transmission electron microscopy. Thicker oxide shells are obtained by oxidation in O2 ambient compared with NO ambient. Oxidation in O2 is observed to be self-limiting at temperatures below the viscoelastic temperature of SiO2 because of compressive stress normal to the SiO2/Si interface, which retards the surface oxidation rate. Oxidation in NO also results in self-limiting oxidation due to the incorporation of N at the Si/SiOx interface. This N-rich interfacial layer acts as an effective barrier against oxidant diffusion and also blocks the reaction sites on the Si surface. Therefore, NO oxidation is successful in slowing further oxidation of Si cores, even in a severe oxidizing ambient such as O2 at 1050 °C. © 2003 American Institute of Physics.
Journal of Applied Physics 04/2003; 93(9):5637-5642. · 2.17 Impact Factor
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ABSTRACT: Thin-film SOI MOSFETs are of interest for scaling devices down into the deep-submicron region due to their ability to reduce short-channel effects (SCE). While double-gate MOSFET is currently considered the most promising candidate for CMOS scaled beyond the 20-30nm limit, we investigate the single-gated SOI MOSFET scalability at the 30nm gate length generation. We have examined their electrostatic behavior using the drift-diffusion ISE DESSIS device simulator. An internally developed quantum transport simulator was also used to confirm the DESSIS simulation trend and assess the impact of thin silicon film on SCE. The device under study has mid-gap workfunction gate material, undoped channel and 15Å gate oxide thickness. This device presents the strongest scaling potential due to the high mobility from the absence of ionized doping impurities, suppression of dopant fluctuation effects and reduced threshold voltage variation with silicon film thickness. We have studied the impact of the silicon film thickness, BOX and front gate dielectric thickness and k values on the short-channel performance of the device. The ground plane structure was also simulated for comparison. We show that extremely thin silicon film thickness around 3nm would be necessary to meet the low-power applications 1999 ITRS specifications at the 50nm technology node. The quantum mechanical effects at this silicon film thickness become dominant, preventing the FDSOI technology to be scaled down to 30nm and beyond.
SOI Conference, IEEE International 2002; 11/2002
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S.B. Samavedam,
L.B. La,
J. Smith,
S. Dakshina-Murthy,
E. Luckowski,
J. Schaeffer,
M. Zavala,
R. Martin,
V. Dhandapani,
D. Triyoso, [......],
J. Mogab,
C. Thomas,
P. Abramowitz,
M. Moosa,
J. Conner,
J. Jiang,
V. Arunachalarn, M. Sadd,
B.-Y. Nguyen,
B. White
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ABSTRACT: We report for the first time on a novel dual-metal gate CMOS integration on HfO/sub 2/ gate dielectric using TiN (PMOS) and TaSiN (NMOS) gate electrodes. Compared to a single metal integration, the dual-metal integration does not degrade gate leakage, mobility and charge trapping behavior. Promising preliminary TDDB data were obtained from dual-metal gate MOSFETs, while still delivering much improved gate leakage (10/sup 4/ - 10/sup 5/ X better than SiO/sub 2/).
Electron Devices Meeting, 2002. IEDM '02. International; 02/2002
