-
Meikei Ieong
[show abstract]
[hide abstract]
ABSTRACT: This paper will review recent progress of innovative devices and materials for nano-CMOS technology. This paper will discuss (1) various mobility enhancement techniques for faster carrier, (2) new materials and structures for device scaling, and (3) novel contact and silicide technology for parasitic resistance reduction.
Nanotechnology Materials and Devices Conference, 2006. NMDC 2006. IEEE; 11/2006
-
Min Yang,
V.W.C. Chan,
K.K. Chan,
L. Shi,
D.M. Fried,
J.H. Stathis,
A.I. Chou,
E. Gusev,
J.A. Ott,
L.E. Burns,
M.V. Fischetti, Meikei Ieong
[show abstract]
[hide abstract]
ABSTRACT: At the onset of innovative device structures intended to extend the roadmap for silicon CMOS, many techniques have been investigated to improve carrier mobility in silicon MOSFETs. A novel planar silicon CMOS structure, seeking optimized surface orientation, and hence carrier mobilities for both nFETs and pFETs, emerged. Hybrid-orientation technology provides nFETs on (100) surface orientation and pFETs on [110] surface orientation through wafer bonding and silicon selective epitaxy. The fabrication processes and device characteristics are reviewed in this paper.
IEEE Transactions on Electron Devices 06/2006; · 2.32 Impact Factor
-
[show abstract]
[hide abstract]
ABSTRACT: Device improvement with strain engineering is considered a way to enhance the carrier mobility. Several stress-transfer techniques (such as etch-stop liner, stress transfer technique, e-SiGe) using extra integration process into an existing baseline process is demonstrated. In addition, new preparation techniques of strained-Si surface (e.g. biaxial tensile stress) and different substrate orientation to enhance mobility are introduced. The challenges and vitality of each method are discussed and compared. In addition, we highlight how the stress oriented from the layout geometry affects the device electrical behavior. The issues and improvement in the circuit level device modeling are discussed.
Custom Integrated Circuits Conference, 2005. Proceedings of the IEEE 2005; 10/2005
-
Qiqing Ouyang,
Min Yang,
J. Holt,
S. Panda,
Huajie Chen,
H. Utomo,
M. Fischetti,
N. Rovedo,
Jinghong Li,
N. Klymko,
H. Wildman,
T. Kanarsky,
G. Costrini,
D.M. Fried,
A. Bryant,
J.A. Ott, Meikei Ieong,
Chun-Yung Sung
[show abstract]
[hide abstract]
ABSTRACT: CMOS devices with embedded SiGe source/drain for pFETs and tensile stressed liner for nFETs have been demonstrated for the first time on hybrid orientation substrates. Ring oscillators have also been fabricated. Significant performance improvement is observed in hybrid orientation substrates compared to (100) control substrates with embedded SiGe.
VLSI Technology, 2005. Digest of Technical Papers. 2005 Symposium on; 07/2005
-
Huiling Shang,
J. Rubino,
B. Doris,
A. Topol,
J. Sleight,
J. Cai,
L. Chang,
A. Ott,
J. Kedzierski,
K. Chan,
L. Shi,
K. Babich,
J. Newbury,
E. Sikorski,
B.N. To,
Y. Zhang,
K.W. Guarini, Meikei Ieong
[show abstract]
[hide abstract]
ABSTRACT: For the first time, we show the experimental inversion mobility data on ultra thin [110] SOI substrates for thickness as thin as 6nm. Both electron and hole mobility in ultra thin [110] SOI are evaluated as a function of SOI thickness. In addition, novel processes such as [110] selective epitaxy and extremely thin cobalt disilicide CoSi<sub>2</sub> are developed. Ring oscillators and SRAM cell are demonstrated for the first time on 6nm [110] ultra thin SOI. When compared to ultra thin SOI in (100) substrate, we observe ∼33% drive current enhancement in PFETs at Lg=50nm and ∼1.8X hole mobility enhancement.
VLSI Technology, 2005. Digest of Technical Papers. 2005 Symposium on; 07/2005
-
[show abstract]
[hide abstract]
ABSTRACT: PFETs with embedded-eSiGe S/D are demonstrated for the first time on rotated wafers with <100> channels. Improved short-channel behavior is achieved. The performance variation is reduced because hole mobility is less sensitive to both transverse and longitudinal stress. Hence, embedded SiGe on rotated wafers have improved robustness for short-channel pFETs.
VLSI Technology, 2005. (VLSI-TSA-Tech). 2005 IEEE VLSI-TSA International Symposium on; 05/2005
-
[show abstract]
[hide abstract]
ABSTRACT: Complete gate silicidation has recently been demonstrated as an excellent technique for the integration of metal gates into MOSFETs. From the various silicide gate materials NiSi has been shown to be the most scalable. In this paper, a versatile method for controlling the workfunction of an NiSi gate is presented. This method relies on doping the poly-Si with various impurities prior to silicidation. The effect of various impurities including B, P, As, Sb, In, and Al is described. The segregation of the impurities from the poly-Si to the silicide interface during the silicidation step is found to cause the NiSi workfunction shift. The effect of the segregated impurities on gate capacitance, mobility, local workfunction stability, and adhesion is studied.
IEEE Transactions on Electron Devices 02/2005; · 2.32 Impact Factor
-
Huiling Shang,
J.O. Chu,
S. Bedell,
E.P. Gusev,
P. Jamison,
Ying Zhang,
J.A. Ott,
M. Copel,
D. Sadana,
K.W. Guarini, Meikei Ieong
[show abstract]
[hide abstract]
ABSTRACT: For the first time, we have integrated strained germanium (s-Ge) channel PMOSFETs with conventional CMOS processes including shallow trench isolation (STI) and scaled thin gate dielectrics. The selectively formed thin s-Ge channels are realized on pre-patterned SiGe on insulator (SGOI) regions by local thermal mixing (TM) or selective UHVCVD process. The thinnest SiO<sub>2</sub> on the s-Ge is achieved by low temperature remote plasma oxidation of a thin Si cap. As a result, 3X drive current enhancement is demonstrated on the fabricated s-Ge channel PMOSFETs over the Si controls. In addition, an appropriate threshold voltage (Vth) is demonstrated on the HfO<sub>2</sub>/P+ poly Si gate PMOSFETs when using an s-Ge channel.
Electron Devices Meeting, 2004. IEDM Technical Digest. IEEE International; 01/2005
-
[show abstract]
[hide abstract]
ABSTRACT: In the next decade, advances in complementary metal-oxide semiconductor fabrication will lead to devices with gate lengths (the region in the device that switches the current flow on and off) below 10 nanometers (nm), as compared with current gate lengths in chips that are now about 50 nm. However, conventional scaling will no longer be sufficient to continue device performance by creating smaller transistors. Alternatives that are being pursued include new device geometries such as ultrathin channel structures to control capacitive losses and multiple gates to better control leakage pathways. Improvement in device speed by enhancing the mobility of charge carriers may be obtained with strain engineering and the use of different crystal orientations. Here, we discuss challenges and possible solutions for continued silicon device performance trends down to the sub-10-nm gate regimes.
Science 01/2005; 306(5704):2057-60. · 31.20 Impact Factor
-
[show abstract]
[hide abstract]
ABSTRACT: Metal-gate FinFETs were fabricated using complete gate silicidation with Ni, combining the advantages of metal-gate and double-gate transistors. NiSi-gate workfunction control is demonstrated using silicide induced impurity segregation of As, P, and B over a range of 400 mV. High device performance is achieved by integrating the NiSi metal gate with an epitaxial raised source/drain, silicided separately with CoSi<sub>2</sub>. Process considerations for this dual silicide integration scheme are discussed. Poly-Si gated FinFETs are also fabricated and used as references for workfunction and transconductance.
IEEE Transactions on Electron Devices 01/2005; · 2.32 Impact Factor
-
[show abstract]
[hide abstract]
ABSTRACT: Conventional scaling is no longer effective to continue device performance trend because of technological difficulties in the scaling of key device parameters. In this paper, we discuss device scaling options beyond convention device structures. We discuss ultrathin body silicon on insulator (UTSOI) MOSFET and FinFET structures for improved electrostatic. We also discuss various mobility enhancement techniques including strained silicon on insulator (SGOI), strained silicon directly on insulator (SSDOI), and hybrid orientation technology (HOT).
Solid-State and Integrated Circuits Technology, 2004. Proceedings. 7th International Conference on; 11/2004
-
[show abstract]
[hide abstract]
ABSTRACT: With the advent of novel device structures that can be easily fabricated outside of the traditional (100) plane, it may be advantageous to change the crystal orientation to optimize CMOS circuit performance. The use of alternative surface orientations such as [110] and (111) enhances hole mobility while degrading electron mobility, thus allowing for adjustment of the ratio between nMOS and pMOS transistor drive currents. By optimizing the surface orientation, up to a 15% improvement in gate delay can be expected. This value depends upon the type of logic gate, the off-state leakage specification, and technology scaling trends. The introduction of high-κ dielectrics may provide an added incentive for the use of non-(100) orientations as this method of circuit performance enhancement may be used to compensate for mobility degradation from the high-κ interface. Additional concerns including layout area and device reliability are discussed.
IEEE Transactions on Electron Devices 11/2004; · 2.32 Impact Factor
-
[show abstract]
[hide abstract]
ABSTRACT: In this letter, we report self-aligned n-channel germanium (Ge) MOSFETs with a thin Ge oxynitride gate dielectric and tungsten gate electrode. Excellent off-state current is achieved through the reduction of junction leakage. For the first time, we have demonstrated an n-channel Ge MOSFET with a subthreshold slope of 150 mV/dec and an on-off current ratio of ∼10<sup>4</sup>.
IEEE Electron Device Letters 04/2004; · 2.85 Impact Factor
-
[show abstract]
[hide abstract]
ABSTRACT: Thin-body fully depleted silicon on insulator (FDSOI) devices with NiSi metal gates were fabricated with gate lengths down to 20 nm. Specific issues in the integration of the NiSi-gated FDSOI devices were investigated, in particular: gate CMP, the phase stability of the nickel silicide, and parasitic resistance.
Electron Devices Meeting, 2003. IEDM '03 Technical Digest. IEEE International; 01/2004
-
[show abstract]
[hide abstract]
ABSTRACT: Three dimensional devices and, integrated circuits are attractive options for overcoming barriers in device and interconnect scaling, offering an opportunity to continue the CMOS performance trend. This paper reviews the process technology and associated design issues in three dimensional devices and integrated circuits.
Custom Integrated Circuits Conference, 2003. Proceedings of the IEEE 2003; 10/2003
-
Min Yang,
E.P. Gusev, Meikei Ieong,
O. Gluschenkov,
D.C. Boyd,
K.K. Chan,
P.M. Kozlowski,
C.P. D'Emic,
R.M. Sicina,
P.C. Jamison,
A.I. Chou
[show abstract]
[hide abstract]
ABSTRACT: Dependence of CMOS performance on silicon crystal orientation of [100], [111], and [110] has been investigated with the equivalent gate dielectric thickness less than 3 nm. Hole mobility enhancement of /spl ges/160% has been observed for both oxynitride and HfO/sub 2/ gate dielectrics on [110] surfaces compared with [100]. CMOS drive current is nearly symmetric on [110] orientation without any degradation of subthreshold slope. For HfO/sub 2/ gate dielectrics, an approximately 68% enhancement of pMOSFET drive current has been demonstrated on [110] substrates at L/sub poly/=0.12 /spl mu/m, while current reduction in nMOS is around 26%.
IEEE Electron Device Letters 06/2003; · 2.85 Impact Factor
-
[show abstract]
[hide abstract]
ABSTRACT: Double gate devices based upon the FinFET architecture are fabricated, with gate lengths as small as 30 nm. Particular attention is given to minimizing the parasitic series resistance. Angled extension implants and selective silicon epitaxy are investigated as methods for minimizing parasitic resistance in FinFETs. Using these two techniques high performance devices are fabricated with on-currents comparable to fully optimized bulk silicon technologies. The influence of fin thickness on device resistance and short channel effects is discussed in detail. Devices are fabricated with fins oriented in the <100> and <100> directions showing different transport properties.
IEEE Transactions on Electron Devices 05/2003; · 2.32 Impact Factor
-
Zhibin Ren,
P.M. Solomon,
T. Kanarsky,
B. Doris,
O. Dokumaci,
P. Oldiges,
R.A. Roy,
E.C. Jones, Meikei Ieong,
R.J. Miller,
W. Haensch,
H.-S.P. Wong
[show abstract]
[hide abstract]
ABSTRACT: This paper presents an experimental examination of hole mobility in ultra-thin body (UTB) SOI MOSFETs, covering wide ranges of T/sub SOI/ (between /spl sim/3.7 nm and /spl sim/50 nm), and temperature (between /spl sim/79 K and /spl sim/320 K). This paper addresses the observed strong degradation of hole mobility at extremely thin T/sub SOI/, proposing an additional surface roughness scattering mechanism for the thinnest samples due to the perturbation of the conducting band potential stemming from spatial confinement.
Electron Devices Meeting, 2002. IEDM '02. International; 02/2002
-
B. Doris, Meikei Ieong,
T. Kanarsky,
Ying Zhang,
R.A. Roy,
O. Dokumaci,
Zhibin Ren,
Fen-Fen Jamin,
Leathen Shi,
W. Natzle,
Hsiang-Jen Huang,
J. Mezzapelle,
A. Mocuta,
S. Womack,
M. Gribelyuk,
E.C. Jones,
R.J. Miller,
H.-S.P. Wong,
W. Haensch
[show abstract]
[hide abstract]
ABSTRACT: We examine the scaling limits for planar single gate technology using the ultra-thin Si channel MOSFET. Characteristics for extreme scaled devices with physical gate lengths down to 6 nm and SOI channels as thin as 4 nm are presented. For the first time, we report ring oscillators with 26 nm gate lengths and ultra-thin Si channels.
Electron Devices Meeting, 2002. IEDM '02. International; 02/2002
-
Solid-State Device Research Conference, 2001. Proceeding of the 31st European; 10/2001
