D.M. Fried

Publications (18)8.02 Total impact

• Conference Proceeding: CMOS Fabricated by Hybrid-Orientation Technology (HOT)

  Bin Yang, M Yang, D.M. Fried, C. D. Sheraw, A Waite, K. Nummy, L. Black, S.D. Kim, H Yin, B Kim, S. Narasimha, X Chen, M. Khare, S. Luning, P. Agnello
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  ABSTRACT: Hybrid-orientation technology (HOT), a novel planar CMOS approach that fabricates NMOS on (100) silicon surface and PMOS on (110) silicon surface to take advantage of the highest carrier mobilities on these surfaces, is reviewed. HOT module process flow, defects formed during the HOT module, HOT CMOS performance enhancement and its layout dependence, as well as the high Rext issue for (110) PMOS are discussed in this paper.
  Electron Devices and Semiconductor Technology, 2007. EDST 2007. Proceeding of 2007 International Workshop on; 07/2007
• Conference Proceeding: Challenges and Opportunities for High Performance 32 nm CMOS Technology

  J. W. Sleight, I. Lauer, O. Dokumaci, D. M. Fried, D. Guo, B. Haran, S. Narasimha, C. Sheraw, D. Singh, M. Steigerwalt, X. Wang, P. Oldiges, D. Sadana, C.Y. Sung, W. Haensch, M. Khare
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  ABSTRACT: Starting with the 45 nm node, a tradeoff between performance and density exists that become more severe at the 32 nm node. An in-depth analysis of the impact of pitch and increased parasitics on device performance in the 32 nm node is presented. To counteract these effects, reduction of parasitics, gate length scaling, and aggressive stress engineering are necessary. Optimized layout using a "relaxed-pitch" approach is demonstrated to show up to a 15% improvement over conventional layout in ring oscillators. The lower parasitics of SOI provide an additional degree of freedom allowing relaxed pitch designs to enhance performance in critical paths. Simpler device isolation in SOI is also shown to be very beneficial in this generation leading to an improved cost/performance tradeoff compared to previous generations
  Electron Devices Meeting, 2006. IEDM '06. International; 01/2007
• Source

  Available from: lw23.com

  Article: Hybrid-orientation technology (HOT): opportunities and challenges

  Min Yang, V.W.C. Chan, K.K. Chan, L. Shi, D.M. Fried, J.H. Stathis, A.I. Chou, E. Gusev, J.A. Ott, L.E. Burns, M.V. Fischetti, Meikei Ieong
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  ABSTRACT: At the onset of innovative device structures intended to extend the roadmap for silicon CMOS, many techniques have been investigated to improve carrier mobility in silicon MOSFETs. A novel planar silicon CMOS structure, seeking optimized surface orientation, and hence carrier mobilities for both nFETs and pFETs, emerged. Hybrid-orientation technology provides nFETs on (100) surface orientation and pFETs on [110] surface orientation through wafer bonding and silicon selective epitaxy. The fabrication processes and device characteristics are reviewed in this paper.
  IEEE Transactions on Electron Devices 06/2006; · 2.32 Impact Factor
• Conference Proceeding: Investigation of CMOS devices with embedded SiGe source/drain on hybrid orientation substrates

  Qiqing Ouyang, Min Yang, J. Holt, S. Panda, Huajie Chen, H. Utomo, M. Fischetti, N. Rovedo, Jinghong Li, N. Klymko, H. Wildman, T. Kanarsky, G. Costrini, D.M. Fried, A. Bryant, J.A. Ott, Meikei Ieong, Chun-Yung Sung
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  ABSTRACT: CMOS devices with embedded SiGe source/drain for pFETs and tensile stressed liner for nFETs have been demonstrated for the first time on hybrid orientation substrates. Ring oscillators have also been fabricated. Significant performance improvement is observed in hybrid orientation substrates compared to (100) control substrates with embedded SiGe.
  VLSI Technology, 2005. Digest of Technical Papers. 2005 Symposium on; 07/2005
• Source

  Available from: columbia.edu

  Conference Proceeding: Stable SRAM cell design for the 32 nm node and beyond

  L. Chang, D.M. Fried, J. Hergenrother, J.W. Sleight, R.H. Dennard, R.K. Montoye, L. Sekaric, S.J. McNab, A.W. Topol, C.D. Adams, K.W. Guarini, W. Haensch
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  ABSTRACT: SRAM cell stability will be a primary concern for future technologies due to variability and decreasing power supply voltages. 6T-SRAM can be optimized for stability by choosing the cell layout, device threshold voltages, and the β ratio. 8T-SRAM, however, provides a much greater enhancement in stability by eliminating cell disturbs during a read access, thus facilitating continued technology scaling. We demonstrate the smallest 6T (0.124μm² half-cell) and full 8T (0.1998μm²) cells to date.
  VLSI Technology, 2005. Digest of Technical Papers. 2005 Symposium on; 07/2005
• Conference Proceeding: Dual stress liner enhancement in hybrid orientation technology

  C.D. Sheraw, M. Yang, D.M. Fried, G. Costrini, T. Kanarsky, W.-H. Lee, V. Chan, M.V. Fischetti, J. Holt, L. Black, [......], D. Chidambarrao, X. Wang, A. Bryant, D. Brown, C.-Y. Sung, P. Agnello, M. Ieong, S.-F. Huang, X. Chen, M. Khare
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  ABSTRACT: Hybrid orientation technology (HOT) has been successfully integrated with a dual stress liner (DSL) process to demonstrate outstanding PFET device characteristics in epitaxially grown [110] bulk silicon. Stress induced by the nitride MOL liners results in mobility enhancement that depends on the designed orientation of the gate, in agreement with theory. Compressive stressed liner films are utilized to increase HOT PFET saturation current to 635 uA/um I_DSat at 100 nA/um I_OFF for V_DD=1.0 V at a 45 nm gate length. The AC performance of a HOT ring oscillator shows 14% benefit from [110] silicon and an additional 8% benefit due to the compressive MOL film.
  VLSI Technology, 2005. Digest of Technical Papers. 2005 Symposium on; 07/2005
• Article: Microlithography 2005

  S. E. Steen, S. J. McNab, L. Sekaric, I. Babich, J. Patel, J. Bucchignano, M. Rooks, D. M. Fried, A. W. Topol, J. R. Brancaccio, R. Yu, J. M. Hergenrother, J. P. Doyle, R. Nunes, R. G. Viswanathan, S. Purushothaman, M. B. Rothwell
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  ABSTRACT: Semiconductor process development teams are faced with increasing process and integration complexity while the time between lithographic capability and volume production has remained more or less constant over the last decade. Lithography tools have often gated the volume checkpoint of a new device node on the ITRS roadmap. The processes have to be redeveloped after the tooling capability for the new groundrule is obtained since straight scaling is no longer sufficient. In certain cases the time window that the process development teams have is actually decreasing. In the extreme, some forecasts are showing that by the time the 45nm technology node is scheduled for volume production, the tooling vendors will just begin shipping the tools required for this technology node. To address this time pressure, IBM has implemented a hybrid-lithography strategy that marries the advantages of optical lithography (high throughput) with electron beam direct write lithography (high resolution and alignment capability). This hybrid-lithography scheme allows for the timely development of semiconductor processes for the 32nm node, and beyond. In this paper we will describe how hybrid lithography has enabled early process integration and device learning and how IBM applied e-beam & optical hybrid lithography to create the world's smallest working SRAM cell.© (2005) COPYRIGHT SPIE--The International Society for Optical Engineering. Downloading of the abstract is permitted for personal use only.
  05/2005;
• Conference Proceeding: Aggressively scaled (0.143 μm2) 6T-SRAM cell for the 32 nm node and beyond

  D.M. Fried, J.M. Hergenrother, A.W. Topol, L. Chang, L. Sekaric, J.W. Sleight, S.J. McNab, J. Newbury, S.E. Steen, G. Gibson, [......], J.A. Ott, C.D. Adams, T.J. Dalton, R. Nunes, D.R. Medeiros, R. Viswanathan, M. Ketchen, M. Ieong, W. Haensch, K.W. Guarini
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  ABSTRACT: A 0.143 μm² 6T-SRAM cell has been fabricated using a planar SOI technology with mixed electron-beam and optical lithography. This is the smallest functional 6T-SRAM cell ever reported - consistent with cell areas beyond the 32 nm technology node. Enabling process features include a 25 nm SOI layer, shallow trench isolation (STI), 45 nm physical gates with ultra-narrow 15 nm spacers, novel extremely thin cobalt disilicide, 50 nm tungsten plug contacts, and damascene copper interconnects. Device threshold voltages (V_T) and cell beta ratio (β) are optimized for cell stability at these aggressive ground rules. The 0.143 μm² 6T-SRAM cell exhibits a static noise margin (SNM) of 148 mV at V^DD=1.0 V.
  Electron Devices Meeting, 2004. IEDM Technical Digest. IEEE International; 01/2005
• Conference Proceeding: On the integration of CMOS with hybrid crystal orientations

  M. Yang, V. Chan, S.H. Ku, M. Ieong, L. Shi, K.K. Chan, C.S. Murthy, R.T. Mo, H.S. Yang, E.A. Lehner, [......], J.R. Holt, S.E. Steen, M.P. Chudzik, D.M. Fried, K. Bernstein, H. Zhu, C.Y. Sung, J.A. Ott, D.C. Boyd, N. Rovedo
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  ABSTRACT: Design and integration issues have been investigated for the hybrid orientation technology (HOT), i.e. device isolation, epitaxy and dopant implantation. Ring oscillators using HOT CMOS have been demonstrated for the first time, with L_poly about 85nm and t_ox=2.2nm, resulting in 21% improvement compared with control CMOS on (100) orientations.
  VLSI Technology, 2004. Digest of Technical Papers. 2004 Symposium on; 07/2004
• Article: High-performance p-type independent-gate FinFETs

  D.M. Fried, J.S. Duster, K.T. Kornegay
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  ABSTRACT: We present, to our knowledge, the first successful integration of two independent gates on a p-type FinFET. These results also represent a significant performance improvement over previously reported Independent-Gate FinFET results. The devices have gate lengths ranging from 0.5 to 5 μm, and designed fin thicknesses ranging from 25 to 75 nm. Electrical results show near-ideal subthreshold slopes in double-gate mode (both gates modulated simultaneously). Independent-Gate operation is also examined by modulating saturated drain current with both front and back-gate voltages independently. The results are compiled to analyze performance trends versus fin thickness and gate length.
  IEEE Electron Device Letters 05/2004; · 2.85 Impact Factor
• Conference Proceeding: Scaling beyond the 65 nm node with FinFET-DGCMOS

  E.J. Nowak, T. Ludwig, I. Aller, J. Kedzierski, M. Leong, B. Rainey, M. Breitwisch, V. Gemhoefer, J. Keinert, D.M. Fried
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  ABSTRACT: Exponential growth in leakage power density with physical scaling is driving ULSI technology towards innovative device architectures. Double-gate CMOS (DGCMOS), achieved through use of the Delta Device (D.Hisamoto et al, IEDM 1989, p.833-836), or FinFET (X.Huang et al, IEDM 1999, p.67-70), provides both a tactical solution to the gate-leakage challenge and a strategic scaling advantage. FinFET fabrication is very close to that of the conventional CMOS process, with only minor disruptions, yielding the potential for a rapid deployment to manufacturing. Planar circuit designs have been converted to FinFET-DGCMOS without disruption to physical area.
  Custom Integrated Circuits Conference, 2003. Proceedings of the IEEE 2003; 10/2003
• Article: Improved independent gate N-type FinFET fabrication and characterization

  D.M. Fried, J.S. Duster, K.T. Kornegay
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  ABSTRACT: N-type independent gate FinFETs (IGFinFETs) have been fabricated and characterized. Previous published results for this structure highlighted processing deficiencies. Several process enhancements have improved device results beyond those previously reported. These process improvements are presented, and the resulting device is demonstrated. Device results for 2 micron channel length devices are shown. Six decades of drain current suppression and low gate leakage currents are achieved. Subthreshold slope of 200 mV/dec and a threshold voltage tuning range of 1.7 V are demonstrated. This device combines the behavioral characteristics of independent-double-gate MOSFETs with the processing advantages and integration of FinFETs.
  IEEE Electron Device Letters 10/2003; · 2.85 Impact Factor
• Conference Proceeding: A Fin-type independent-double-gate NFET

  D.M. Fried, E.J. Nowak, J. Kedzierski, J.S. Duster, K.T. Komegay
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  ABSTRACT: We present, to our knowledge, the first published experimental integration of two independent gates on a FinFET. The devices have symmetric gate oxide physical thicknesses of 8.5 nm, gate lengths ranging from 0.25 μm to 5 μm, and designed fin thicknesses ranging from 10 nm to 100 nm. Independent-gate operation is demonstrated by modulating saturated drain current with both front and back gate voltages.
  Device Research Conference, 2003; 07/2003
• Conference Proceeding: Demonstration of FinFET CMOS circuits

  B.A. Rainey, D.M. Fried, M. Ieong, J. Kedzierski, E.J. Nowak
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  ABSTRACT: We present, to our knowledge, the first published experimental demonstration of a CMOS inverter chain built from FinFETs, completely integrated in 180nm CMOS technology, using one level of copper wiring and tungsten vias. A four-stage inverter chain with Lgate = 200nm, Tsi =, 60nm, and Tox = 2.2nm was run at 1.5V. We demonstrate successfully propagating CMOS levels through four inverter stages employing over 300 fins.
  Device Research Conference, 2002. 60th DRC. Conference Digest; 02/2002
• Conference Proceeding: A functional FinFET-DGCMOS SRAM cell

  E.J. Nowak, B.A. Rainey, D.M. Fried, J. Kedzierski, M. Ieong, W. Leipold, J. Wright, M. Breitwisch
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  ABSTRACT: An operational six-transistor SRAM cell is experimentally demonstrated using Double Gate CMOS FinFET technology. A cell size of 4.8 μm² was achieved in 180 nm node technology, with stable operation at 1.5 V using a single level of copper interconnect. To our knowledge this represents the first experimental demonstration of a fully integrated FinFET SRAM Cell.
  Electron Devices Meeting, 2002. IEDM '02. International; 02/2002
• Conference Proceeding: A sub 40-nm body thickness n-type FinFET

  D.M. Fried, A.P. Johnson, E.J. Nowak, J.H. Rankin, C.R. Willets
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  ABSTRACT: Summary form only given. We experimentally demonstrate near-ideal subthreshold behavior of fully-depleted fin-style double-gate n-type MOSFETs and the best measured transconductance Gm-sat = 72 S/m (>400 S/m intrinsic) for sub-40 nm n-type FinFETs reported. This silicon nFET exhibits experimental ideality n = 1.13, in good agreement with the deviation from unity expected due only to source/drain coupling. These results comprise the best behavior for 100 nm-scale double-gate nFETs in terms of channel subthreshold characteristics and gate leakage observed experimentally to date. Hisamoto et al. (1989) introduced experimental results on doubld-gate silicon MOSFETs in which the channel is formed by etching single-crystal silicon to leave a vertical fin standing, forming a gate which wraps around the fin, with source and drain regions on the two ends of the fin. This basic idea was further refined to sub-50 nm n-type MOSFETs and then extended to sub-50 nm p-type MOSFETs. Using simplified fabrication techniques, we demonstrate improved behavior, from an intrinsic channel point of view, of the nFET work, using conventional CMOS integration on n-type FinFETs
  Device Research Conference, 2001; 02/2001
• Conference Proceeding: High-performance symmetric-gate and CMOS-compatible Vt asymmetric-gate FinFET devices

  J. Kedzierski, D.M. Fried, E.J. Nowak, T. Kanarsky, J.H. Rankin, H. Hanafi, W. Natzle, D. Boyd, Ying Zhang, R.A. Roy, [......], C.P. Willets, A. Johnson, S.P. Cole, H.E. Young, N. Carpenter, D. Rakowski, B.A. Rainey, P.E. Cottrell, M. Ieong, H.-S.P. Wong
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  ABSTRACT: Double-gate FinFET devices with asymmetric and symmetric polysilicon gates have been fabricated. Symmetric gate devices show drain currents competitive with fully optimized bulk silicon technologies. Asymmetric-gate devices show |V_t|~0.1 V, with off-currents less than 100 nA/um at V_gs=0
  Electron Devices Meeting, 2001. IEDM Technical Digest. International; 02/2001
• Conference Proceeding: Integration of Local Stress Techniques with Strained-Si Directly on Insulator (SSDOI) Substrates

  Haizhou Yin, Z. Ren, H. Chen, J. Holt, X. Liu, J.W. Sleight, K. Rim, V. Chan, D.M. Fried, Y.H. Kim, J.O. Chu, B.J. Greene, S.W. Bedell, G. Pfeiffer, R. Bendernagel, D.K. Sadana, T. Kanarsky, C.Y. Sung, M. Ieong, G. Shahidi
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  ABSTRACT: Various local stress techniques have been integrated on strained-Si directly on insulator (SSDOI) substrates, including dual stress liner (DSL), stress memory technique (SMT), and embedded SiGe (eSiGe) in source/drain. SMT shows mild drive current enhancement on nFETs. PFETs with eSiGe exhibit significant enhancement, suggesting eSiGe compatibility with SSDOI is excellent. A ring oscillator delay of 3ps is achieved at leakage current of 1 muA/mum and V_DD=1.1V
  VLSI Technology, 2006. Digest of Technical Papers. 2006 Symposium on;