Hsin-Chou Chi

National Dong Hwa University, Hua-lien, Taiwan, Taiwan

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Publications (10)0.74 Total impact

  • Hsin-Chou Chi, Tat-Seng Chang, Chia-Ming Wu
    IEEE Fifth International Symposium on Industrial Embedded Systems - SIES 2010, University of Trento, Italy, July 7-9, 2010; 01/2010
  • Source
    Etri Journal 01/2009; 31(2):111-120. · 0.74 Impact Factor
  • Hsin-Chou Chi, Chia-Ming Wu, Jun-Hui Lee
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    ABSTRACT: Network-on-chip (NoC) architectures provide a high-performance communication infrastructure for system-on-chip designs. Circuit-switched networks guarantee transmission latency and throughput, and hence are suitable for NoC architectures with real-time traffic. In this paper, we propose an efficient integrated scheme which automatically maps application tasks onto NoC tiles, establishes communication paths, and allocates a proper bandwidth for each communication path. Simulation results show that our design provides an effective solution for a critical step in the NoC design. The cost and latency of the switch in the circuit-switched network can be lowered down with our scheme.
    Electronic Design, Test and Applications, 2008. DELTA 2008. 4th IEEE International Symposium on; 02/2008
  • Hsin-Chou Chi, Chia-Ming Wu
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    ABSTRACT: Circuit-switched networks provide guaranteed transmission latency and throughput, and hence are suitable for many network-on-chip (NoC) architectures requiring quality-of-service. A circuit-switched on-chip network needs a scheduler to arrange communication paths and allocate a proper bandwidth for each path. Such a scheduler offers an effective solution for a critical step in the NoC design. In this paper, we propose an efficient scheduler for pre-scheduled circuit-switched on-chip networks. Based on simulations, we show that low delivery latency for circuit-switched on-chip networks can be achieved with our scheduler. Furthermore, with efficient scheduling, the cost of the switches can be also minimized
    IFIP VLSI-SoC 2006, IFIP WG 10.5 International Conference on Very Large Scale Integration of System-on-Chip, Nice, France, 16-18 October 2006; 01/2006
  • Hsin-Chou Chi, Chia-Ming Wu, Sung-Tze Wu
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    ABSTRACT: In this paper, the design of a hybrid switch for on-chip networks in SoC design is presented. This hybrid switch provides both guaranteed and best-effort communication services for network-on-chip architectures. We use the pre-scheduled circuit-switched network to support guaranteed communication service between IPs on the chip. In order to fully utilize the network bandwidth, we further incorporate the packet-switched architecture. Our design has been experimentally implemented using UMC 0.18 mum technology. It has an aggregate bandwidth of 5 times 434MHz times 64 bits = 139 Gb/s. Compared to previous designs, our switch provides high performance with a reasonable cost
    Design and Diagnostics of Electronic Circuits and systems, 2006 IEEE; 01/2006
  • Chia-Ming Wu, Hsin-Chou Chi, Ying-Ming Huang
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    ABSTRACT: Network-on-chip (NoC) design provides designers a communication infrastructure to integrate heterogeneous intellectual property (IP) cores. To reuse IPs based on shared buses in the NoC architecture, an interface is needed for the NoC communication protocol. In this paper, we present a wrapper design for low-power error-correcting data delivery in on-chip networks. Our wrapper not only provides an interface for reusing IP cores based on the AMBA bus, but also lowers down power dissipation and improves robustness of data transmission. We have implemented this IP wrapper using cell-based design with UMC 0.18 mum technology. It shows that the wrapper design is feasible and efficient.
    01/2006;
  • Chia-Ming Wu, Hsin-Chou Chi
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    ABSTRACT: System-on-a-chip (SoC) designs provide designers to integrate dozens of heterogeneous IP blocks together by a dedicated interconnect network. The major problems in the ultra deep sub-micron technology SoC design arise from the interconnection networks, such as non-scalable global wire delay, failure to achieve global synchronization, and errors due to signal integrity issues. These problems might be mitigated by the network-on-chip (NoC) approach based on regular on-chip communication networks. In this paper, the authors propose the pre-scheduled circuit-switched network for NoC architectures. The authors have designed the switch supporting the network. Such architectures based on circuit switching with efficient buffer management can achieve guaranteed transmission latencies
    Asian Solid-State Circuits Conference, 2005; 12/2005
  • Chia-Ming Wu, Hsin-Chou Chi, Ming-Chao Lee
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    ABSTRACT: In this paper, we propose a scheme that automatically maps IP cores onto the network-on-chip architecture in SoC design. Our algorithm provides an efficient solution for satisfying design constraints, bandwidth of links, latency of communication paths, and average communication traffic. Two regular topologies, including mesh and torus, are assumed for the network. The X-Y routing and adaptive routing schemes are used to simulate the network for our algorithm. Experimental results show that our proposed algorithm decreases the required bandwidth of links compared to existing algorithms
    ASIC, 2005. ASICON 2005. 6th International Conference On; 11/2005
  • Hsin-Chou Chi, Yu-Seng Lin, Chia-Ming Wu
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    ABSTRACT: Not Available
    Circuits and Systems, 2004. Proceedings. The 2004 IEEE Asia-Pacific Conference on; 01/2005
  • Hsin-Chou Chi, Chia-Ming Wu
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    ABSTRACT: System-on-a-chip (SoC) has emerged to become a cost-effective approach for embedded systems design with rapid advance of semiconductor technology. It allows designers to integrate a number of heterogeneous IP blocks together based on a system interconnect. However, traditional dedicated wiring as the system interconnect has many shortcomings, such as non-scalable global wire delay, failure to achieve global synchronization, and errors due to signal integrity issues. These problems can be mitigated by the network-on-chip (NoC) architecture based on regular on-chip communication networks. In this paper, we present three efficient switch designs for NoC systems based on circuiting switching. Such switch designs with efficient buffer management can provide the on-chip network with guaranteed throughput and transmission latencies.
    Embedded and Ubiquitous Computing - EUC 2005, International Conference EUC 2005, Nagasaki, Japan, December 6-9, 2005, Proceedings; 01/2005