Hsin-Chou Chi

National Dong Hwa University, Hua-lien, Taiwan, Taiwan

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Publications (17)0.95 Total impact

  • Hsin-Chou Chi, Hsi-Che Tseng, Chia-Wei Jeng
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    ABSTRACT: One of the major problems with advanced semiconductor technology is timing errors caused by process variation and device aging. With such problems, conventional worst-case designs suffer poor system performance. This paper proposes an aggressive design technique for VLSI digital filters for tolerating timing errors. When a timing error occurs, the system reconfigures the buffer cell of the problematic stage with little performance degradation. We have applied the technique to several digital filters. The design of an IIR filter with tolerance of timing errors is described and demonstrated. The results show that our proposed design achieves tolerance of multiple timing errors with small cost of chip area and power consumption.
    Consumer Electronics (GCCE), 2013 IEEE 2nd Global Conference on; 01/2013
  • Hsin-Chou Chi, Fen Ferng, Yu-Chen Hsieh
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    ABSTRACT: Network-on-chip (NoC) architectures have been recently proposed as the communication framework for large-scale chips. A well-designed NoC architecture can facilitate the IP cores to communicate with each other efficiently. In this paper, we propose a systematic mapping scheme, called area utilization based mapping (AUBM), to map the IP cores from the communication core graph to the mesh network. In AUBM, the IP cores can be of various sizes. Extensive experiments have been conducted for evaluating the mapping schemes. AUBM is compared with previously proposed schemes for different applications as well as synthetic workloads. Our experiment results show that AUBM outperforms others in almost all cases in terms of the mapping cost involving traffic volume and chip area.
    High Performance Computing and Communication & 2012 IEEE 9th International Conference on Embedded Software and Systems (HPCC-ICESS), 2012 IEEE 14th International Conference on; 01/2012
  • Hsin-Chou Chi, Hsi-Che Tseng, Chih-Ling Yang
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    ABSTRACT: System-on-a-chip (SoC) as a platform for system integration has been used extensively in modern VLSI design. The IEEE P1500 has been proposed as a standard for the challenging SoC testing problem. In order to improve the correctness of SoC testing, the IEEE P1500 hardware itself should be tested and diagnosed first before using it. This paper proposes an efficient design-for-diagnosability architecture for the IEEE P1500 and evaluates its performance. Effective diagnosis procedures are presented and the response sequences of the output are analyzed for fault diagnosis. With our proposed designs, single stuck-at faults and fault location can be efficiently determined.
    Proceedings of the 2nd IEEE International Conference on Networked Embedded Systems for Enterprise Applications, NESEA 2011, Perth, Australia, December 8-9, 2011; 01/2011
  • Hsin-Chou Chi, Hsi-Che Tseng, Kun-Lin Tsai
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    ABSTRACT: With semiconductor technology scaling, the size of transistors and their operating voltage keep decreasing. One of the major problems with advanced semiconductor technology is timing errors caused by process variation and noises. With such problem, conventional worst-case designs suffer poor system performance. This paper proposes aggressive designs of systolic arrays for matrix multiplication which can tolerate timing errors. When timing errors occur, the system reconfigures the computing cells with little performance degradation. Our implementation results show that our proposed designs achieve tolerance of timing errors with reasonable cost.
  • Hsin-Chou Chi, Tat-Seng Chang, Chia-Ming Wu
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    ABSTRACT: Network-on-chip (NoC) architectures have been recently proposed as the communication framework for large-scale chips. The design of the routing system for the packet-switched on-chip network is one of the critical issues for the success of NoC architectures. In this paper, we present the design of a reconfigurable pipelined switch for mesh on-chip networks. When the switch is in the regular mode for the regular mesh, the routing is equivalent to the XY routing. When there are faulty links or switches, the switch is reconfigured in irregular mode for faulty mesh networks. The routing decision hardware in the switch is efficiently implemented based on a simple distance calculation algorithm. Our switch design is validated by implementation of four different versions with 64-bit, 128-bit, 256-bit, and 512-bit links, respectively. Our results show that our routing decision can be efficiently realized with distance calculation hardware.
    IEEE Fifth International Symposium on Industrial Embedded Systems - SIES 2010, University of Trento, Italy, July 7-9, 2010; 01/2010
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    ABSTRACT: Network-on-chip (NoC) architecture provides a highper-formance communication infrastructure for system-on-chip designs. Circuit-switched networks guarantee transmission latency and throughput; hence, they are suitable for NoC architecture with real-time traffic. In this paper, we propose an efficient integrated scheme which automatically maps application tasks onto NoC tiles, establishes communication circuits, and allocates a proper bandwidth for each circuit. Simulation results show that the average waiting times of packets in a switch in 6, , and mesh NoC networks are 0.59, 0.62, and 0.61, respectively. The latency of circuits is significantly decreased. Furthermore, the buffer of a switch in NoC only needs to accommodate the data of one time slot. The cost of the switch in the circuit-switched network can be reduced using our scheme. Our design provides an effective solution for a critical step in NoC design.
    Etri Journal 04/2009; 31(2):111-120. DOI:10.4218/etrij.Apr2009.RP080608 · 0.95 Impact Factor
  • Hsin-Chou Chi, Hsi-Che Tseng, Chih-Ling Yang
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    ABSTRACT: Locating the scan chain fault is a critical step for IC manufacturers to analyze failure for yield improvement. In this paper, we propose a diagnosis scheme to locate the single stuck-at fault in scan chains. Our diagnosis scheme is an improved design to a previously proposed scheme which can diagnose the output of each cell flip-flop in the scan chain. With our scheme, not only the output of each cell flip-flop can be diagnosed, but also the inverse output of each cell flip-flop and the serial input of the scan chain as well. Our proposed diagnosis scheme is efficient and takes (4n+6) clock cycles in the worst case for an n-bit scan chain.
    43rd Annual Conference on Information Sciences and Systems, CISS 2009, The John Hopkins University, Baltimore, MD, USA, 18-20 March 2009; 04/2009
  • Hsin-Chou Chi, Chia-Ming Wu, Jun-Hui Lee
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    ABSTRACT: Network-on-chip (NoC) architectures provide a high-performance communication infrastructure for system-on-chip designs. Circuit-switched networks guarantee transmission latency and throughput, and hence are suitable for NoC architectures with real-time traffic. In this paper, we propose an efficient integrated scheme which automatically maps application tasks onto NoC tiles, establishes communication paths, and allocates a proper bandwidth for each communication path. Simulation results show that our design provides an effective solution for a critical step in the NoC design. The cost and latency of the switch in the circuit-switched network can be lowered down with our scheme.
    Electronic Design, Test and Applications, 2008. DELTA 2008. 4th IEEE International Symposium on; 02/2008
  • Hsin-Chou Chi, Chia-Ming Wu
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    ABSTRACT: Circuit-switched networks provide guaranteed transmission latency and throughput, and hence are suitable for many network-on-chip (NoC) architectures requiring quality-of-service. A circuit-switched on-chip network needs a scheduler to arrange communication paths and allocate a proper bandwidth for each path. Such a scheduler offers an effective solution for a critical step in the NoC design. In this paper, we propose an efficient scheduler for pre-scheduled circuit-switched on-chip networks. Based on simulations, we show that low delivery latency for circuit-switched on-chip networks can be achieved with our scheduler. Furthermore, with efficient scheduling, the cost of the switches can be also minimized
    IFIP VLSI-SoC 2006, IFIP WG 10.5 International Conference on Very Large Scale Integration of System-on-Chip, Nice, France, 16-18 October 2006; 01/2006
  • Chia-Ming Wu, Hsin-Chou Chi, Ying-Ming Huang
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    ABSTRACT: Network-on-chip (NoC) design provides designers a communication infrastructure to integrate heterogeneous intellectual property (IP) cores. To reuse IPs based on shared buses in the NoC architecture, an interface is needed for the NoC communication protocol. In this paper, we present a wrapper design for low-power error-correcting data delivery in on-chip networks. Our wrapper not only provides an interface for reusing IP cores based on the AMBA bus, but also lowers down power dissipation and improves robustness of data transmission. We have implemented this IP wrapper using cell-based design with UMC 0.18 mum technology. It shows that the wrapper design is feasible and efficient.
  • Hsin-Chou Chi, Chia-Ming Wu, Sung-Tze Wu
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    ABSTRACT: In this paper, the design of a hybrid switch for on-chip networks in SoC design is presented. This hybrid switch provides both guaranteed and best-effort communication services for network-on-chip architectures. We use the pre-scheduled circuit-switched network to support guaranteed communication service between IPs on the chip. In order to fully utilize the network bandwidth, we further incorporate the packet-switched architecture. Our design has been experimentally implemented using UMC 0.18 mum technology. It has an aggregate bandwidth of 5 times 434MHz times 64 bits = 139 Gb/s. Compared to previous designs, our switch provides high performance with a reasonable cost
    Design and Diagnostics of Electronic Circuits and systems, 2006 IEEE; 01/2006
  • Chia-Ming Wu, Hsin-Chou Chi
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    ABSTRACT: System-on-a-chip (SoC) designs provide designers to integrate dozens of heterogeneous IP blocks together by a dedicated interconnect network. The major problems in the ultra deep sub-micron technology SoC design arise from the interconnection networks, such as non-scalable global wire delay, failure to achieve global synchronization, and errors due to signal integrity issues. These problems might be mitigated by the network-on-chip (NoC) approach based on regular on-chip communication networks. In this paper, the authors propose the pre-scheduled circuit-switched network for NoC architectures. The authors have designed the switch supporting the network. Such architectures based on circuit switching with efficient buffer management can achieve guaranteed transmission latencies
    Asian Solid-State Circuits Conference, 2005; 12/2005
  • Chia-Ming Wu, Hsin-Chou Chi, Ming-Chao Lee
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    ABSTRACT: In this paper, we propose a scheme that automatically maps IP cores onto the network-on-chip architecture in SoC design. Our algorithm provides an efficient solution for satisfying design constraints, bandwidth of links, latency of communication paths, and average communication traffic. Two regular topologies, including mesh and torus, are assumed for the network. The X-Y routing and adaptive routing schemes are used to simulate the network for our algorithm. Experimental results show that our proposed algorithm decreases the required bandwidth of links compared to existing algorithms
    ASIC, 2005. ASICON 2005. 6th International Conference On; 11/2005
  • Hsin-Chou Chi, Yu-Seng Lin, Chia-Ming Wu
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    ABSTRACT: Not Available
    Circuits and Systems, 2004. Proceedings. The 2004 IEEE Asia-Pacific Conference on; 01/2005
  • Hsin-Chou Chi, Chia-Ming Wu
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    ABSTRACT: System-on-a-chip (SoC) has emerged to become a cost-effective approach for embedded systems design with rapid advance of semiconductor technology. It allows designers to integrate a number of heterogeneous IP blocks together based on a system interconnect. However, traditional dedicated wiring as the system interconnect has many shortcomings, such as non-scalable global wire delay, failure to achieve global synchronization, and errors due to signal integrity issues. These problems can be mitigated by the network-on-chip (NoC) architecture based on regular on-chip communication networks. In this paper, we present three efficient switch designs for NoC systems based on circuiting switching. Such switch designs with efficient buffer management can provide the on-chip network with guaranteed throughput and transmission latencies.
    Embedded and Ubiquitous Computing - EUC 2005, International Conference EUC 2005, Nagasaki, Japan, December 6-9, 2005, Proceedings; 01/2005
  • Hsin-Chou Chi, Wen-Jen Wu
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    ABSTRACT: High-throughput low-latency interconnection networks are suitable for workstation clusters. An interconnection network can be constructed in different topologies. Typically, interconnection networks with regular topologies, such as mesh, torus, and hypercube, are less scalable for workstation clusters than those with irregular topologies. There have been many deadlock-free routing algorithms developed for regular networks, but it is relatively difficult to solve deadlock problems for irregular networks. We have previously proposed an effective routing scheme, called TRAIN, for irregular networks. The TRAIN routing algorithm is deadlock-free and requires no routing tables in the switch. This routing algorithm is based on a spanning tree which is constructed in the network. In this paper, we study how to construct a spanning tree so that the network can benefit from the TRAIN routing algorithm. Several schemes of constructing spanning trees are studied. These tree construction schemes are evaluated and compared in unloaded networks based on static analysis. They are also evaluated for loaded networks based on simulations.
    Parallel, Distributed and Network-Based Processing, 2003. Proceedings. Eleventh Euromicro Conference on; 03/2003
  • Hsin-Chou Chi, Wen-Jen Wu
    11th Euromicro Workshop on Parallel, Distributed and Network-Based Processing (PDP 2003), 5-7 February 2003, Genova, Italy; 01/2003