Z. Tokei

imec Belgium, Louvain, Flanders, Belgium

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Publications (75)23.33 Total impact

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    ABSTRACT: In-situ electromigration tests have been performed inside a scanning electron microscope on 30 nm wide single damascene interconnects without vias, where a good resolution was obtained and drift velocities during void growth could be measured at 300 °C. These tests showed direct evidence that the cathode end of the line, where a polycrystalline grain cluster encounters a bigger grain, can act as a flux divergent point of Cu diffusion. Moreover, it was found that a thicker barrier suppresses barrier/interface diffusivity of Cu atoms, thereby slowing down electromigration-induced void growth. It was also demonstrated that Cobalt based metal caps are beneficial to electromigration for advanced interconnects where thinner barriers are required.
    Journal of Applied Physics 01/2014; 115(7):074305-074305-6. · 2.21 Impact Factor
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    ABSTRACT: Chip Package Interaction (CPI) gained a lot of importance in the last years. The reason is twofold. First, advanced node IC technologies requires dielectrics in the BEOL (back-end-of-line) with a decreasing value for the dielectric constant k. These so-called (ultra) low-k materials have a reduced stiffness and reduced adhesion strength to the barrier materials, making the BEOL much more vulnerable to externally applied mechanical stress due to packaging. Secondly, advanced packaging technologies such as 3D stacked IC’s use thinned dies (down to 25 μm) which can cause much higher stresses at transistor level, resulting in electron mobility shifts of the transistors. Also the copper TSV (through-silicon-via) generates local stress which affects the device performance. This paper considers both the packaging impact on BEOL integrity and transistor mobility shifts for 3D stacked IC (integrated circuit) technologies.
    Microelectronics Reliability 01/2014; · 1.14 Impact Factor
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    ABSTRACT: In order to enable an oxide-free Cu-to-Cu bonding in a (dual) damascene process, 3-aminopropyltrimethoxysilane- and decanethiol-derived self-assembled monolayers are selectively deposited in a dielectric-Cu based metal–insulator–metal (MIM) capacitor used as a test vehicle, which represents a dual damascene architecture environment. A two-steps SAM coating sequence is investigated for this purpose. In a first step, a “sacrificial” SHSAM is deposited on the Cu areas at the bottom of the vias. In a second step, a “barrier” NH2SAM is deposited on the dielectric areas in the field region and via’s sidewalls. This deposition sequence followed by the selective thermal ablation of the “sacrificial” SAM vs. the “barrier” SAM, enable an oxide-free Cu-to-Cu connection at via’s bottom. The differential in thermal stability between the amino and thiol SAMs has been studied by water contact angle and cyclic voltammetry. While the sacrificial SAM is selectively desorbed by thermal ablation already at ∼200 °C, the barrier SAM on the dielectric sidewall and field regions withstands a thermal budget as high as ∼350 °C. The substrate-selective SAMs depositions are revealed by XPS chemical characterization on the Cu and dielectric areas of the MIM structures supported by the SEM visualization of the Au nanoparticles that selectively decorate the NH2 functionalities of the barrier SAM.
    Microelectronic Engineering 06/2013; 106:76–80. · 1.22 Impact Factor
  • Microelectronic Engineering 01/2013; · 1.22 Impact Factor
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    ABSTRACT: From the 32nm CMOS node on, trench shaped local interconnects are introduced to connect the individual transistors on a chip. Aggressive pitch scaling and overlay errors however challenge the integrity of the SiN dielectric between the gate and the local interconnects. In this work we study the reliability of this dielectric. It is found that the current between gate and the contacts is polarity independent and the breakdown voltage shows a strong polarity dependence. While within die good uniformity is observed, due to overlay errors the spacing between the gate and the contact varies across the wafer. This results in large VBD and tBD variability and for an intrinsic TDDB lifetime extrapolation correction for this non-uniformity required.
    Reliability Physics Symposium (IRPS), 2013 IEEE International; 01/2013
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    ABSTRACT: Over 40 months of low field BEOL TDDB data obtained on different test vehicles with spacings ranging from 90-30nm and OSG low-k dielectrics with k-values ranging from 3.22.0 are summarized. For the dielectrics with k≥2.5, a simultaneous maximum likelihood fit with a fixed acceleration factor and varying distributional shapes is performed. By considering the log-likelihood of each model fit, this approach allows a comparison of fitted lifetime models. This approach also allows estimating the parameters of the impact damage model, which is more difficult to fit due to its multiple acceleration factors. From a statistical point of view and by using a 95% significance level, the results show that the power law and the impact damage model equally outperform all other proposed models and that their prediction to lower fields are very similar. As from a practical point of view the power law model is much more easy to use due to its limited number of fitting parameters, we propose to use the power law model for low-k dielectrics with k-value between 2.5 and 3.2. Regardless of the presence of a protection film, our low-field data obtained on the k=2.0 material show different acceleration factors at high and low fields. This suggests that different breakdown mechanisms are present at different fields and that, in order to allow reliable predictions to operating fields, future TDDB tests of highly porous films will require stresses at much wider field ranges.
    Reliability Physics Symposium (IRPS), 2013 IEEE International; 01/2013
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    ABSTRACT: The method “trap spectroscopy by charge injection and sensing” (TSCIS) is applied to porous SiOCH low-k dielectrics integrated in MIS capacitors with Ta based diffusion barriers. Most of the low-k samples show an unexpected negative flatband voltage shift with charge injection, which we attribute to positive charge built up in the bulk low-k due to Ta penetration. The only porous low-k sample that can be fitted using the standard TSCIS method is a k=2.0 material in combination with a low pore penetration barrier. The fitted trap distribution demonstrates a low trap density and an amorphous structure. It is also shown that UV treatment can change the low-k charge trapping behavior.
    Reliability Physics Symposium (IRPS), 2013 IEEE International; 01/2013
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    ABSTRACT: We investigate void nucleation and growth during electromigration in 30 nm half pitch Cu lines. Diffusion interfaces are varied a) by using SiCN dielectric cap or a CoWP metal cap and b) by tuning the thickness of TaN/Ta barrier metal. The developed local sense EM test method and in-situ EM observations allow understanding void nucleation and growth stages. For the SiCN cap, independent of barrier thickness, there are two void growth modes sensitive to grain structure. In contrast, for the CoWP cap, a single mode independent of the grain structure is observed, where a nucleated void is pinned in the test line. We also show that Co diffuses into the interface between the barrier metal and Cu, and suppresses Cu diffusivity at that interface. As both Cu diffusivities at the cap and barrier interfaces are suppressed by the presence of Co, a CoWP cap is beneficial to electromigration for advanced interconnects where thinner barrier metals are required.
    Interconnect Technology Conference (IITC), 2013 IEEE International; 01/2013
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    ABSTRACT: CVD Mn-based self-formed barrier (SFB) has been evaluated and integrated for reliability and RC delay assessment. Intrinsic TDDB lifetimes were extracted from planar capacitor measurement. A comparable lifetime as the TaN/Ta reference was obtained on SiO2 and porous low-k with a thin oxide liner. Good reliability performance was demonstrated after integration. Compared to conventional barrier, significant RC reduction (up to 45% at 40nm half pitch) and lower via resistance which become more beneficial upon scaling present CVD Mn-based SFB as an attractive candidate for future interconnect technology.
    Interconnect Technology Conference (IITC), 2013 IEEE International; 01/2013
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    ABSTRACT: The intrinsic effects of current crowding and current density gradients on electromigration in back end of line copper interconnects have been investigated using a simple single layer test structure, where the electromigration performance of standard straight structures is compared to structures with a 90° angle. Using finite element modeling, it is demonstrated that locally higher current crowding and current density gradients are indeed present in these angled structures. As electromigration lifetimes are comparable between the straight and the angled structures and no void formation is observed in or close to the angle, we conclude that the intrinsic impact of current crowing and current density gradients in via-electromigration is negligible.
    Reliability Physics Symposium (IRPS), 2013 IEEE International; 01/2013
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    ABSTRACT: The dielectric breakdown field (EBD) and the time-dependent-dielectric-breakdown (TDDB) of eight different low-K films with porosities between 3% (K=3.2) and 50% (K=1.8) and thicknesses between 15 and 60 nm were investigated using imec's planar capacitors (p-cap) test vehicle. EBD values decrease linearly with porosity to reach 6MV/cm at 50% porosity. The analogous Organo-Silicate Glass (OSG) films show a similar field acceleration factors independently of porosity. An OSG 2.0 film with 45% porosity and a periodic mesoporous organosilica (PMO) 1.8 film, both sealed with 12-nm OSG 3.0 sealing also showed the same field acceleration factor. On the other hand, the corresponding Weibull slopes vary and decrease linearly with porosity, which is in agreement with the percolation model. Also, the Weibull slopes decrease linearly with dielectric thickness. Extrapolating those data and analyzing the maximum allowed electrical fields to meet 10-years lifetime (EMAX), critical dielectric spacing are discussed as a function of porosity. It is shown that for 20-nm spacing remedial measures are required for porosities >30%.
    Reliability Physics Symposium (IRPS), 2013 IEEE International; 01/2013
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    ABSTRACT: We discuss the improvement in the electrical characterization and the performance of 150 nm diameter contacts filled with carbon nanotubes (CNT) and a Cu damascene top metal on 200mm wafers. The excellent agreement between the yield curves for the parallel and single contacts shows that a reliable electrical characterization is obtained. We demonstrate that integration changes improved the resistivity of the CNT contact significantly by reducing it from 11.8·103 μΩ·cm down to 5.1·103 μΩ·cm. Finally, a length scaling of the CNT contacts was used to find the individual contributors to the lowering of the single CNT contact resistance.
    Interconnect Technology Conference (IITC), 2013 IEEE International; 01/2013
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    ABSTRACT: The residual stresses generated during different processing steps and during thermal cycling of 3D stack packages, mimicking its service life, are quantified by Finite Element Modeling (FEM) together with measurements of dedicated FET arrays used as CPI sensors. Thermo-mechanical deformation of the package can be directly transferred to the Cu/low-k interconnect, inducing large local stresses to drive interfacial crack formation and propagation. The test vehicle used in this work is an imec's proprietary logic CMOS IC on top of which a commercial DRAM is stacked. Different test structures contained in the chip, allow monitoring thermo-mechanical stresses and electrical characteristics of TSV's and micro-bumps. It is shown that FET current shifts can be used to measure the stress in the surface of the chip. The use of standard FEM approach is insufficient to simulate the CPI due to the large dimensional difference between the packaging and interconnects structures. Due to size and speed limitations of commercial computers, a 3D thermo mechanical model of a 3D package cannot contain all the details from the package and at the same time simulate the small structures such as metal and dielectric layers in the BEOL. For this reason, multi-scale simulations are the best choice for identifying the critical regions of the package where high stresses and/or delamination failures are expected to occur. We have shown the methodology to follow to study the CPI.
    Electronics Packaging Technology Conference (EPTC); 12/2012
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    ABSTRACT: Due to their large volume and close proximity to devices, the reliability of copper TSV's is a concern, both with respect to mechanical stresses induced by the TSV in the Si and with respect to copper drift into the liner and the Si. This abstract summarizes recent achievements obtained in imec's 3D-reliability work package where above mentioned reliability concerns are evaluated in detail. To study the impact of mechanical stresses induced by the TSV in the Si, the saturation drain currents Id of transistors have been used as stress sensors. The offset of the Id of transistors closer to a TSV with respect to transistors far away from a TSV has been studied, both directly after processing and after thermal storage and thermal shock. It is shown that stresses generated by the TSV in the Si increase after thermal storage above certain temperatures while thermal shock reduces these stresses. The first is attributed to stress relaxation at high temperatures, while the latter is attributed to cracking/delamination at critical interfaces. To study continuity in TSV-barriers, a method, further referred to as dual ramp rate IVctrl, is introduced. The method consists of controlled current-voltage sweeps at different rates. The difference in breakdown fields for different ramp rates allows estimating TDDB (=Time Dependent Dielectric Breakdown) field acceleration parameters. Applying a negative voltage to the TSV (-V) does not allow copper to drift into the liner, while when applying a positive voltage (+V) to the TSV, copper can drift into the liner in case of a defective, non-continuous barrier. Comparing TDDB field acceleration parameters of -V versus +V tests gives insight in barrier properties. In our study, weak reliability is observed in systems where the TSV-barriers are not continuous.
    Physical and Failure Analysis of Integrated Circuits (IPFA); 07/2012
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    ABSTRACT: The early detection of Cu sub-surface voids in nano-interconnects has become a main challenge with the reduction of the critical dimensions of the interconnects. A new methodology for full wafer Cu void inspection with high sensitivity and high speed has been developed using a Multi-Purpose SEM (MP-SEM) using high accelerating voltage, high resolution and multi BSE detectors. This inspection methodology has been used to evaluate the Cu metallization quality in nanointerconnects. The effectiveness of this inspection methodology was proven through the evidence of relations between Cu void density, trench widths, pattern density, and surrounding dummy structures.
    Proc SPIE 03/2012;
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    ABSTRACT: The time dependent dielectric breakdown (TDDB) of four organo-silicate-glass (OSG) films with varying porosity (k=2.0, 2.5, 2.8 & 3.0) was investigated using metal-insulator-semiconductor (MIS) capacitors. Without any barrier, the dielectrics show lower TDDB-lifetimes under Cu ion drift conditions, where the OSG-2.8-film exhibits a better performance. Other results are that the damage caused by TaN/Ta barriers doesn't significantly change the TDDB performance and that the OSG-2.0-film showed excellent TDDB lifetimes.
    Interconnect Technology Conference (IITC), 2012 IEEE International; 01/2012
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    ABSTRACT: Small EM voids in 30nm wide polycrystalline Cu lines which are formed earlier than full voids are characterized using local sense EM test structure. The growth of these initial voids is stopped after a rapid 1-10 Ohm resistance increase. The void mechanism follows a proposed model of polycrystalline Cu grain depletion. It is also shown that by detecting the initial voids, simple and cost effective single level Cu lines can be a promising test method to assess EM reliability in the early stages of process development for scaled Cu interconnects.
    Reliability Physics Symposium (IRPS), 2012 IEEE International; 01/2012
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    ABSTRACT: Electromigration failure times of 100 nm wide dual damascene Cu interconnects have been evaluated over a very wide range of different stages of void formation and growth. Voids that did not span the whole line width and height have been monitored using the so-called local sense structures, while standard single via structures were used to study fully grown voids. The activation energy Ea did not change over the whole experimental range of failure times indicating that the main diffusion path during void formation and growth does not change in our semi-bamboo lines. The earlier reported increase in distributional spread σ after full void formation is less pronounced during void formation which is due to different kinetics before and after full void formation. The use of defining failure criteria before full void formation has been explored as a tool to reduce electromigration test times. Due to the constant Ea, test times can be reduced by over a factor of two.
    Reliability Physics Symposium (IRPS), 2012 IEEE International; 01/2012
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    ABSTRACT: This paper discusses the electrical and structural characterization of 150 nm diameter contacts filled with carbon nanotubes (CNTs) and a Cu damascene top metal. We present the first images of CNTs in direct contact with the top metal. A CNT tip clean before metallization reduced the single CNT contact hole resistance from 4.8 kΩ down to 2.8 kΩ (aspect ratio 2.4). The first basic electrical breakdown experiments with Kelvins resulted in high breakdown currents of 5-13 MA/cm2.
    Interconnect Technology Conference (IITC), 2012 IEEE International; 01/2012
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    ABSTRACT: The aim of this paper is to predict the performance of local interconnects, manufactured by advanced patterning options as double patterning and EUV lithography. Electrical wire parameters as resistance, capacitance, RC delay and coupling between adjacent wires are extracted by simulation from scaled 2-D interconnect models, calibrated with dimensions and electrical parameters measured on simple test structures. CD and overlay variations of each patterning option are estimated from experimental and ITRS data and are included in the models. The extracted wire parameters allow the comparison between the patterning options and indicate the optimal choice for the next technology nodes.
    Interconnect Technology Conference (IITC), 2012 IEEE International; 01/2012