Z. Tokei

imec Belgium, Louvain, Flanders, Belgium

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Publications (90)25.26 Total impact

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    ABSTRACT: Nominal LG VFET-based RO may operate up to ~60% faster than LFET-based RO at the same energy per switch for both 7nm and 5nm technology nodes depending on the layout and BEOL-load. With VFETs, relaxing the LG is possible and it results in an extra 27% in IEFF in comparison to the nominal LG case. In addition, VFETs enable different layouts, which can be used to optimize performance under certain BEOL-load. Introduction of VFETs is more favorable at the 5nm node than at the 7nm node. As such, VFETs show a performance competitive path for continued scaling beyond 7nm technologies.
    2014 72nd Annual Device Research Conference (DRC); 06/2014
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    ABSTRACT: Different advanced patterning schemes have been compared with respect to the effect of line-overlay and via-misalignment on dielectric reliability, where the effects on the Weibull slope, on the TDDB lifetime and on Vmax were studied. The patterning schemes compared in this study are litho-etch-litho-etch and self-aligned-double-patterning. For typical intrinsic reliability parameters, in comparison with the ideal case of 0nm line-overlay and via-misalignment, the self-aligned-double-patterning scheme with a 3σ via-misalignment of 6nm leads to a Vmax reduction of 26%. The additional line-overlay errors that must be taken into account for the litho-etch-litho-etch patterning scheme leads to a reduction of Vmax by 43%.
    2014 IEEE International Reliability Physics Symposium (IRPS); 06/2014
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    ABSTRACT: Different approaches combining Finite Element Simulations and in-situ electrical measurement of stress sensors during a BABSI test are proven to be ideal combination to quantitatively compare the strength of BEOL layers. It is shown that detectable mechanical failures during a shear or BABSI test are insufficient to detect early opens of the metal interconnections. A good agreement was found between the applied loads to the BEOL stack, the response of stress sensors below the Cu pillar and finite element simulations. Next, the risk of cohesive and adhesive failures in the Cu/low-k layers is evaluated in function of stiffness of low-k and design of metal interconnections.
    2014 IEEE International Reliability Physics Symposium (IRPS); 06/2014
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    ABSTRACT: Chip Package Interaction (CPI) gained a lot of importance in the last years. The reason is twofold. First, advanced node IC technologies requires dielectrics in the BEOL (back-end-of-line) with a decreasing value for the dielectric constant k. These so-called (ultra) low-k materials have a reduced stiffness and reduced adhesion strength to the barrier materials, making the BEOL much more vulnerable to externally applied mechanical stress due to packaging. Secondly, advanced packaging technologies such as 3D stacked IC’s use thinned dies (down to 25 μm) which can cause much higher stresses at transistor level, resulting in electron mobility shifts of the transistors. Also the copper TSV (through-silicon-via) generates local stress which affects the device performance. This paper considers both the packaging impact on BEOL integrity and transistor mobility shifts for 3D stacked IC (integrated circuit) technologies.
    Microelectronics Reliability 06/2014; · 1.14 Impact Factor
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    ABSTRACT: The scaling challenges of STT-MRAM read operation down to sub-20nm is discussed. Various contributing factors to the MTJ cell resistance variation were investigated with focus on MRAM cell variation due to lithography patterning technique and interconnects. With EUV SADP or single print process, the MRAM cell size can be scaled down to 18nm physical dimension with 4.2% sigma/ave cell area variation. For interconnects, the increasing resistance variation with shrinking dimensions poses most of the challenges.
    2014 IEEE International Interconnect Technology Conference / Advanced Metallization Conference (IITC/AMC); 05/2014
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    ABSTRACT: The properties of alternative metals to Cu and W for interconnect applications are reviewed based on first-principles simulations and benchmarked in terms of intrinsic bulk resistivity and electromigration.
    2014 IEEE International Interconnect Technology Conference / Advanced Metallization Conference (IITC/AMC); 05/2014
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    ABSTRACT: We discuss the selection criteria for alternative metals in order to fulfill the requirements necessary for interconnects at half pitch values below 10 nm. The performance of scaled interconnects using transition metal germanides and CoAl alloys as metallization are studied and compared to conventional Cu and W interconnects.
    2014 IEEE International Interconnect Technology Conference / Advanced Metallization Conference (IITC/AMC); 05/2014
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    ABSTRACT: A carbon nanotube (CNT) contact length scaling is used to derive the electron mean-free path (λCNT) after full integration. A CNT-to-metal contact resistance of 76 Ω and lower was obtained for 150 nm diameter contacts. By estimating the number of conducting walls in the CNT bundle, a λCNT of 74 nm is found, which is longer than for Cu. We propose a more conservative approach of calculating λCNT solely from electrical data. The result is that our CNT interconnects have ballistic transport over 24 nm, which is 5 times longer than reported so far.
    2014 IEEE International Interconnect Technology Conference / Advanced Metallization Conference (IITC/AMC); 05/2014
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    ABSTRACT: In this paper we present our methodology to establish a quantitative comparison of the induced stresses at different locations of the package and their effect on the strength of the back-end-of-line (BEOL). A Chip Stack Package (CSP) with tight pitch and lead free solder joints is used as test vehicle. Different configurations of the interconnection between the solder balls and the BEOL, including a stiff passivation layer combined with a polyimide stress buffer layer with different thickness and openings are analyzed. It was found that the bending moment of the outermost solder joint induces high tensile stresses in the BEOL layer and this stress is reduced by increasing the thickness of the passivation layer. For this particular case, an optimal geometry of the stress buffer, in terms of thickness and open diameter is proposed. The stresses and energy release rate (ERR) induced on the BEOL is analyzed in a 2 metal layer configuration with different densities of via interconnections. The strength of the BEOL is improved when increasing both, the stiffness of the low-k material and the density of vias.
    2014 15th International Conference on Thermal, Mechanical and Multi-Physics Simulation and Experiments in Microelectronics and Microsystems (EuroSimE); 04/2014
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    ABSTRACT: Line Edge Roughness (LER) correlation improves the interconnect Time-Dependent Dielectric Breakdown (TDDB) lifetime significantly with respect to non-correlated interconnect based on simulation [M. Stucchi, P. Roussel, Z. Tokei, S. Demuynck, G. Groeseneken, IEEE Trans. Device Mater. Reliab. 99 (2011)] [1]. On the other hand, 50% Line Edge Roughness (LER) correlation has been observed experimentally after spacer formation in 20nm half pitch (HP) interconnects using a Spacer-Defined Double Patterning (SDDP) approach. Comparisons of breakdown field distribution and TDDB lifetime for SDDP patterned 20nm HP and Litho-Etch-Litho-Etch (LELE) patterned 35nm HP Cu interconnect confirm that the SDDP approach offers potential benefits for TDDB lifetime, which enable future interconnect scaling.
    Microelectronic Engineering 12/2013; 112:116-120. · 1.22 Impact Factor
  • 224th ECS Meeting; 10/2013
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    ABSTRACT: In order to enable an oxide-free Cu-to-Cu bonding in a (dual) damascene process, 3-aminopropyltrimethoxysilane- and decanethiol-derived self-assembled monolayers are selectively deposited in a dielectric-Cu based metal–insulator–metal (MIM) capacitor used as a test vehicle, which represents a dual damascene architecture environment. A two-steps SAM coating sequence is investigated for this purpose. In a first step, a “sacrificial” SHSAM is deposited on the Cu areas at the bottom of the vias. In a second step, a “barrier” NH2SAM is deposited on the dielectric areas in the field region and via’s sidewalls. This deposition sequence followed by the selective thermal ablation of the “sacrificial” SAM vs. the “barrier” SAM, enable an oxide-free Cu-to-Cu connection at via’s bottom. The differential in thermal stability between the amino and thiol SAMs has been studied by water contact angle and cyclic voltammetry. While the sacrificial SAM is selectively desorbed by thermal ablation already at ∼200 °C, the barrier SAM on the dielectric sidewall and field regions withstands a thermal budget as high as ∼350 °C. The substrate-selective SAMs depositions are revealed by XPS chemical characterization on the Cu and dielectric areas of the MIM structures supported by the SEM visualization of the Au nanoparticles that selectively decorate the NH2 functionalities of the barrier SAM.
    Microelectronic Engineering 06/2013; 106:76–80. · 1.22 Impact Factor
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    ABSTRACT: It is demonstrated that the widely used equation to derive the adhesive strength from the external load in a 4 point bending test has a certain error by taking only the substrate’s elastic parameters into account. Next to this, failure location analysis gives insight on the measured variation of adhesive strength for the same interface. Subsequently, with numerical simulations, the adhesive strength can be separated in its different energy modes, allowing a better understanding and characterization of the experimental observations (e.g. higher cohesive energy for increasing low-k stiffness). Finally, the competing failure mechanisms within the BEOL are identified as necessary qualifiers for BEOL failure assessment, where currently adhesion strength is mainly used for ranking the performance of different BEOL interfaces.
    Eurosime; 04/2013
  • Conference Paper: IC-package interaction
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    ABSTRACT: Chip Package Interaction (CPI) gained a lot of importance in the last years. The reason is twofold. First, advanced node IC technologies requires dielectrics in the BEOL (back-end-of-line) with a decreasing k value. These so-called (ultra) low-k materials have a reduced stiffness and adhesion strength to the barrier materials, making the BEOL much more vulnerable to externally applied stress due to packaging. Secondly, advanced packaging technologies such as 3D stacked IC’s use thinned dies (down to 25µm) which can cause much higher stresses at transistor level, resulting in mobility shifts
    Eurosime; 04/2013
  • [Show abstract] [Hide abstract]
    ABSTRACT: Chip Package Interaction (CPI) gained a lot of importance in the last years. The reason is twofold. First, advanced node IC technologies requires dielectrics in the BEOL (back-end-of-line) with a decreasing k value. These so-called (ultra) low-k materials have a reduced stiffness and adhesion strength to the barrier materials, making the BEOL much more vulnerable to externally applied stress due to packaging. Secondly, advanced packaging technologies such as 3D stacked IC’s use thinned dies (down to 25µm) which can cause much higher stresses at transistor level, resulting in mobility shifts
    MAM; 03/2013
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    ABSTRACT: Over 40 months of low field BEOL TDDB data obtained on different test vehicles with spacings ranging from 90-30nm and OSG low-k dielectrics with k-values ranging from 3.22.0 are summarized. For the dielectrics with k≥2.5, a simultaneous maximum likelihood fit with a fixed acceleration factor and varying distributional shapes is performed. By considering the log-likelihood of each model fit, this approach allows a comparison of fitted lifetime models. This approach also allows estimating the parameters of the impact damage model, which is more difficult to fit due to its multiple acceleration factors. From a statistical point of view and by using a 95% significance level, the results show that the power law and the impact damage model equally outperform all other proposed models and that their prediction to lower fields are very similar. As from a practical point of view the power law model is much more easy to use due to its limited number of fitting parameters, we propose to use the power law model for low-k dielectrics with k-value between 2.5 and 3.2. Regardless of the presence of a protection film, our low-field data obtained on the k=2.0 material show different acceleration factors at high and low fields. This suggests that different breakdown mechanisms are present at different fields and that, in order to allow reliable predictions to operating fields, future TDDB tests of highly porous films will require stresses at much wider field ranges.
    Reliability Physics Symposium (IRPS), 2013 IEEE International; 01/2013
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    ABSTRACT: The method “trap spectroscopy by charge injection and sensing” (TSCIS) is applied to porous SiOCH low-k dielectrics integrated in MIS capacitors with Ta based diffusion barriers. Most of the low-k samples show an unexpected negative flatband voltage shift with charge injection, which we attribute to positive charge built up in the bulk low-k due to Ta penetration. The only porous low-k sample that can be fitted using the standard TSCIS method is a k=2.0 material in combination with a low pore penetration barrier. The fitted trap distribution demonstrates a low trap density and an amorphous structure. It is also shown that UV treatment can change the low-k charge trapping behavior.
    Reliability Physics Symposium (IRPS), 2013 IEEE International; 01/2013
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    ABSTRACT: We investigate void nucleation and growth during electromigration in 30 nm half pitch Cu lines. Diffusion interfaces are varied a) by using SiCN dielectric cap or a CoWP metal cap and b) by tuning the thickness of TaN/Ta barrier metal. The developed local sense EM test method and in-situ EM observations allow understanding void nucleation and growth stages. For the SiCN cap, independent of barrier thickness, there are two void growth modes sensitive to grain structure. In contrast, for the CoWP cap, a single mode independent of the grain structure is observed, where a nucleated void is pinned in the test line. We also show that Co diffuses into the interface between the barrier metal and Cu, and suppresses Cu diffusivity at that interface. As both Cu diffusivities at the cap and barrier interfaces are suppressed by the presence of Co, a CoWP cap is beneficial to electromigration for advanced interconnects where thinner barrier metals are required.
    Interconnect Technology Conference (IITC), 2013 IEEE International; 01/2013
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    ABSTRACT: CVD Mn-based self-formed barrier (SFB) has been evaluated and integrated for reliability and RC delay assessment. Intrinsic TDDB lifetimes were extracted from planar capacitor measurement. A comparable lifetime as the TaN/Ta reference was obtained on SiO2 and porous low-k with a thin oxide liner. Good reliability performance was demonstrated after integration. Compared to conventional barrier, significant RC reduction (up to 45% at 40nm half pitch) and lower via resistance which become more beneficial upon scaling present CVD Mn-based SFB as an attractive candidate for future interconnect technology.
    Interconnect Technology Conference (IITC), 2013 IEEE International; 01/2013
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    ABSTRACT: The intrinsic effects of current crowding and current density gradients on electromigration in back end of line copper interconnects have been investigated using a simple single layer test structure, where the electromigration performance of standard straight structures is compared to structures with a 90° angle. Using finite element modeling, it is demonstrated that locally higher current crowding and current density gradients are indeed present in these angled structures. As electromigration lifetimes are comparable between the straight and the angled structures and no void formation is observed in or close to the angle, we conclude that the intrinsic impact of current crowing and current density gradients in via-electromigration is negligible.
    Reliability Physics Symposium (IRPS), 2013 IEEE International; 01/2013

Publication Stats

230 Citations
25.26 Total Impact Points

Institutions

  • 2001–2014
    • imec Belgium
      • Smart Systems and Energy Technology
      Louvain, Flanders, Belgium
  • 2009
    • Newcastle University
      • School of Electrical and Electronic Engineering
      Newcastle upon Tyne, ENG, United Kingdom
  • 2006
    • Cistim Leuven vzw
      Louvain, Flanders, Belgium