Z. Tokei

imec Belgium, Louvain, Flemish, Belgium

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Publications (73)24.81 Total impact

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    ABSTRACT: In recent year, two innovative strategies have been proposed to decrease plasma-induced low-k damage: the P4 approach [Frot et al., 2011] and the cryogenic etch approach [Zhang et al., 2013]. The P4 or “pore stuffing” uses an extrinsic sacrificial pore filler, allowing protection during plasma etching and metallization steps. The cryogenic etch is based on in-situ pore filling by etch byproducts and/or SiOFx sidewall passivation. In this work, a PMO spin-on material with pristine k = 2.31 from SBA has been integrated on 300mm wafers. The integration vehicle uses narrow-spacing structures, i.e. 30nm low-k lines at 180nm pitch. For the cryogenic etch approach, after lithography, the SiC/SOC/SOG hardmask is trimmed and opened using standard etch. Low-k etching is performed by means of a SF6-based plasma chemistry in an ICP chamber equipped with a liquid-N2 cooled substrate holder set at a base temperature of -120°C. Careful optimization of etch conditions allows to considerably decrease the loss of Si-CH3 bonds, keeping an acceptable etch rate, good hardmask selectivity, and reduced bottom roughness. After patterning and subsequent byproduct removal by annealing, a conventional Cu metallization is performed using TaNTa barrier, Cu seed and electroplating. After chemical-mechanical polishing (CMP) and SiC passivation, functional circuits gave integrated dielectric constant of kint = 2.38, i.e. showing a Δk = 0.07 relative to pristine. For the pore stuffing approach, PMMA was used as filling material and driven in after low-k deposition. Due to thermal instability of PMMA, a low-temperature Si3N4 hardmask was used, as well as low-temperature TaNTa barrier. PMMA was removed after CMP, by means of He-H2 downstream plasma ashing or thermal decomposition. Functional circuits gave integrated dielectric constants kint = 2.73 (thermal unstuffing) and kint = 3.14 (He-H2 ashing). By comparison of both approaches, it is observed that pore stuffing increases interconnect flow complexity, by the addition of stuffing and unstuffing steps which can also damage the low-k material; however post-etch surfaces are smooth and barrier metal penetration is suppressed. The pore stuffing approach could be improved by using more thermally stable polymers and the search for damage-free unstuffing methods. The current cryogenic etch process requires only minor changes into the process flow, however currently it requires a base temperature of -120°C. The cryogenic etch process could be improved by the use of plasma additives enhancing by-products condensation and/or pre-condensation steps. We acknowledge support from the European Union under grant agreement No. 318804 (SNM).
    AVS 61st International Symposium & Exhibition, Electronic Materials and Processing; 11/2014
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    ABSTRACT: Nominal LG VFET-based RO may operate up to ~60% faster than LFET-based RO at the same energy per switch for both 7nm and 5nm technology nodes depending on the layout and BEOL-load. With VFETs, relaxing the LG is possible and it results in an extra 27% in IEFF in comparison to the nominal LG case. In addition, VFETs enable different layouts, which can be used to optimize performance under certain BEOL-load. Introduction of VFETs is more favorable at the 5nm node than at the 7nm node. As such, VFETs show a performance competitive path for continued scaling beyond 7nm technologies.
    2014 72nd Annual Device Research Conference (DRC); 06/2014
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    ABSTRACT: Degradation and breakdown mechanisms of a SiOCH low-k material with k=2.3 (25% porosity) and thicknesses ranging from 90nm to 20nm were investigated. By combining time dependent dielectric breakdown (TDDB) data at positive/negative bias stress with thickness scaling results, dielectric failure is proven to be intrinsic and not influenced by copper drift or barrier deposition induced dielectric damage, which is further demonstrated by a very low TDDB thermal activation energy. During dielectric degradation, low field leakage current increase is suggested to be caused by donor type trap generation. It is shown that stress induced leakage current (SILC) can be used as a measure of dielectric degradation. Therefore, by monitoring SILC, low field lifetime can be safely estimated using extrapolation. Based on our experimental results, it is suggested that the impact damage model has a better accuracy for low field lifetime prediction.
    2014 IEEE International Reliability Physics Symposium (IRPS); 06/2014
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    ABSTRACT: Chip Package Interaction (CPI) gained a lot of importance in the last years. The reason is twofold. First, advanced node IC technologies requires dielectrics in the BEOL (back-end-of-line) with a decreasing value for the dielectric constant k. These so-called (ultra) low-k materials have a reduced stiffness and reduced adhesion strength to the barrier materials, making the BEOL much more vulnerable to externally applied mechanical stress due to packaging. Secondly, advanced packaging technologies such as 3D stacked IC’s use thinned dies (down to 25 μm) which can cause much higher stresses at transistor level, resulting in electron mobility shifts of the transistors. Also the copper TSV (through-silicon-via) generates local stress which affects the device performance. This paper considers both the packaging impact on BEOL integrity and transistor mobility shifts for 3D stacked IC (integrated circuit) technologies.
    Microelectronics Reliability 06/2014; DOI:10.1016/j.microrel.2014.02.026 · 1.43 Impact Factor
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    ABSTRACT: The properties of alternative metals to Cu and W for interconnect applications are reviewed based on first-principles simulations and benchmarked in terms of intrinsic bulk resistivity and electromigration.
    2014 IEEE International Interconnect Technology Conference / Advanced Metallization Conference (IITC/AMC); 05/2014
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    ABSTRACT: Cu wire resistance reduction using CVD Mn-based Self-Formed Barrier (SFB) compared to conventional PVD barrier was investigated at 40 and 100 nm half pitch (HP). Mn-based SFB leads to both (1) maximum fractional Cu area in the trenches and (2) Cu resistivity reduction at scaled dimensions. This represents a breakthrough for future interconnect scaling. Blanket Cu experiments suggest that the Cu resistivity reduction in the case of Mn-based SFB can be attributed to lower surface scattering at the dielectric/Cu interface. Finally, promising reliability has been demonstrated in 20 nm HP single damascene (SD) SiO2 trenches integrated with Mn-based SFB.
    2014 IEEE International Interconnect Technology Conference / Advanced Metallization Conference (IITC/AMC); 05/2014
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    ABSTRACT: Continuous decrease of feature size of transistors in accordance with Moore’s law leads to the fact that ultra low-k materials (k < 2.5) should be used for technology nodes beyond 22 nm to maintain IC performance. Spin-on periodic mesoporous oxides (PMO) are considered as promising materials, due to the alkyl bridging reinforcing the matrix and giving exceptionally good mechanical properties and chemical resistance. Damage during plasma etching remains however a major concern for material integration, due to the very porous nature of the low-k [1]. In recent year, two innovative strategies have been proposed to decrease plasma-induced damage: the Post Porosity Plasma Protection or P4 approach by Frot et al. [2], and the cryogenic etch approach by Zhang et al. [3]. The P4 approach uses a extrinsic sacrificial filler, suppressing the porosity of the low-k film, allowing protection during plasma etching and subsequent metallization steps, but requires major changes and additional steps to be added into the interconnect process flow. The cryogenic etch approaches is simpler, since it is based on intrinsic pore filling by etch byproducts condensation and SiOFx sidewall passivation [3]. In this work, a k=2.3 PMO spin-on material from SBA inc. has been integrated using the cryogenic etch approach on 300mm substrates. The integration vehicle uses narrow-spacing structures, i.e. 30nm low-k lines at 180nm pitch, using a SiC/SOC/SOG hardmask. PMO is spin-coated, followed by a soft-bake at 150° C, then a hard-bake is performed at 400° C under N2 ambient for porogen removal and matrix hardening. After hardmask deposition and lithography, the hardmask is trimmed and opened using conventional (room temperature) plasma etching. Low-k etching is then performed by means of a SF6-based plasma chemistry in an ICP chamber equipped with variable temperature substrate holder covering an extended range going from -140° C to +20° C. Optimal base temperature as well as careful optimization of etch conditions (plasma power, bias voltage, pressure, chemistry) allows to considerably decrease the loss of Si-CH3 bonds, keeping an acceptable etch rate, good hardmask selectivity, reduced bottom roughness and negligible moisture absorption. After patterning and subsequent byproduct removal by annealing, a conventional Cu metallization is performed using TaNTa barrier, Cu seed and Cu electroplating. After chemical-mechanical polishing and SiC passivation, functional circuits gave integrated dielectric constant of keff = 2.38, i.e. showing a Δk = 0.07 relative to pristine reference.
    MRS Spring Meeting Symposium CC: New Materials and Processes for Interconnects, Novel Memory and Advanced Display Technologies, San Francisco; 04/2014
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    ABSTRACT: In-situ electromigration tests have been performed inside a scanning electron microscope on 30 nm wide single damascene interconnects without vias, where a good resolution was obtained and drift velocities during void growth could be measured at 300 °C. These tests showed direct evidence that the cathode end of the line, where a polycrystalline grain cluster encounters a bigger grain, can act as a flux divergent point of Cu diffusion. Moreover, it was found that a thicker barrier suppresses barrier/interface diffusivity of Cu atoms, thereby slowing down electromigration-induced void growth. It was also demonstrated that Cobalt based metal caps are beneficial to electromigration for advanced interconnects where thinner barriers are required.
    Journal of Applied Physics 02/2014; 115(7):074305-074305-6. DOI:10.1063/1.4866330 · 2.19 Impact Factor
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    ABSTRACT: In order to enable an oxide-free Cu-to-Cu bonding in a (dual) damascene process, 3-aminopropyltrimethoxysilane- and decanethiol-derived self-assembled monolayers are selectively deposited in a dielectric-Cu based metal–insulator–metal (MIM) capacitor used as a test vehicle, which represents a dual damascene architecture environment. A two-steps SAM coating sequence is investigated for this purpose. In a first step, a “sacrificial” SHSAM is deposited on the Cu areas at the bottom of the vias. In a second step, a “barrier” NH2SAM is deposited on the dielectric areas in the field region and via’s sidewalls. This deposition sequence followed by the selective thermal ablation of the “sacrificial” SAM vs. the “barrier” SAM, enable an oxide-free Cu-to-Cu connection at via’s bottom. The differential in thermal stability between the amino and thiol SAMs has been studied by water contact angle and cyclic voltammetry. While the sacrificial SAM is selectively desorbed by thermal ablation already at ∼200 °C, the barrier SAM on the dielectric sidewall and field regions withstands a thermal budget as high as ∼350 °C. The substrate-selective SAMs depositions are revealed by XPS chemical characterization on the Cu and dielectric areas of the MIM structures supported by the SEM visualization of the Au nanoparticles that selectively decorate the NH2 functionalities of the barrier SAM.
    Microelectronic Engineering 06/2013; 106:76–80. DOI:10.1016/j.mee.2012.12.028 · 1.34 Impact Factor
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    ABSTRACT: From the 32nm CMOS node on, trench shaped local interconnects are introduced to connect the individual transistors on a chip. Aggressive pitch scaling and overlay errors however challenge the integrity of the SiN dielectric between the gate and the local interconnects. In this work we study the reliability of this dielectric. It is found that the current between gate and the contacts is polarity independent and the breakdown voltage shows a strong polarity dependence. While within die good uniformity is observed, due to overlay errors the spacing between the gate and the contact varies across the wafer. This results in large VBD and tBD variability and for an intrinsic TDDB lifetime extrapolation correction for this non-uniformity required.
    Reliability Physics Symposium (IRPS), 2013 IEEE International; 01/2013
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    ABSTRACT: We discuss the improvement in the electrical characterization and the performance of 150 nm diameter contacts filled with carbon nanotubes (CNT) and a Cu damascene top metal on 200mm wafers. The excellent agreement between the yield curves for the parallel and single contacts shows that a reliable electrical characterization is obtained. We demonstrate that integration changes improved the resistivity of the CNT contact significantly by reducing it from 11.8·103 μΩ·cm down to 5.1·103 μΩ·cm. Finally, a length scaling of the CNT contacts was used to find the individual contributors to the lowering of the single CNT contact resistance.
    Interconnect Technology Conference (IITC), 2013 IEEE International; 01/2013
  • K. Croes · Y. Li · M. Lofrano · C.J. Wilson · Z. Tokei
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    ABSTRACT: The intrinsic effects of current crowding and current density gradients on electromigration in back end of line copper interconnects have been investigated using a simple single layer test structure, where the electromigration performance of standard straight structures is compared to structures with a 90° angle. Using finite element modeling, it is demonstrated that locally higher current crowding and current density gradients are indeed present in these angled structures. As electromigration lifetimes are comparable between the straight and the angled structures and no void formation is observed in or close to the angle, we conclude that the intrinsic impact of current crowing and current density gradients in via-electromigration is negligible.
    Reliability Physics Symposium (IRPS), 2013 IEEE International; 01/2013
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    ABSTRACT: We investigate void nucleation and growth during electromigration in 30 nm half pitch Cu lines. Diffusion interfaces are varied a) by using SiCN dielectric cap or a CoWP metal cap and b) by tuning the thickness of TaN/Ta barrier metal. The developed local sense EM test method and in-situ EM observations allow understanding void nucleation and growth stages. For the SiCN cap, independent of barrier thickness, there are two void growth modes sensitive to grain structure. In contrast, for the CoWP cap, a single mode independent of the grain structure is observed, where a nucleated void is pinned in the test line. We also show that Co diffuses into the interface between the barrier metal and Cu, and suppresses Cu diffusivity at that interface. As both Cu diffusivities at the cap and barrier interfaces are suppressed by the presence of Co, a CoWP cap is beneficial to electromigration for advanced interconnects where thinner barrier metals are required.
    Interconnect Technology Conference (IITC), 2013 IEEE International; 01/2013
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    ABSTRACT: CVD Mn-based self-formed barrier (SFB) has been evaluated and integrated for reliability and RC delay assessment. Intrinsic TDDB lifetimes were extracted from planar capacitor measurement. A comparable lifetime as the TaN/Ta reference was obtained on SiO2 and porous low-k with a thin oxide liner. Good reliability performance was demonstrated after integration. Compared to conventional barrier, significant RC reduction (up to 45% at 40nm half pitch) and lower via resistance which become more beneficial upon scaling present CVD Mn-based SFB as an attractive candidate for future interconnect technology.
    Interconnect Technology Conference (IITC), 2013 IEEE International; 01/2013
  • K. Croes · P. Roussel · Y. Barbarin · C. Wu · Y. Li · J. Bommels · Z. Tokei
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    ABSTRACT: Over 40 months of low field BEOL TDDB data obtained on different test vehicles with spacings ranging from 90-30nm and OSG low-k dielectrics with k-values ranging from 3.22.0 are summarized. For the dielectrics with k≥2.5, a simultaneous maximum likelihood fit with a fixed acceleration factor and varying distributional shapes is performed. By considering the log-likelihood of each model fit, this approach allows a comparison of fitted lifetime models. This approach also allows estimating the parameters of the impact damage model, which is more difficult to fit due to its multiple acceleration factors. From a statistical point of view and by using a 95% significance level, the results show that the power law and the impact damage model equally outperform all other proposed models and that their prediction to lower fields are very similar. As from a practical point of view the power law model is much more easy to use due to its limited number of fitting parameters, we propose to use the power law model for low-k dielectrics with k-value between 2.5 and 3.2. Regardless of the presence of a protection film, our low-field data obtained on the k=2.0 material show different acceleration factors at high and low fields. This suggests that different breakdown mechanisms are present at different fields and that, in order to allow reliable predictions to operating fields, future TDDB tests of highly porous films will require stresses at much wider field ranges.
    Reliability Physics Symposium (IRPS), 2013 IEEE International; 01/2013
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    ABSTRACT: Air gap (AG) interconnects, with an ideal dielectric constant k of 1, is a promising approach to reduce signal propagation delay. In this paper, a comparative study of AG and dielectric copper damascene interconnect structures is performed through Raphael (TM) electric field simulation to investigate the capacitance benefit of introducing AG when scaling to small dimensions. The variation in total capacitance as a function of half pitch is simulated for different AG integration schemes proposed in the literature. Ideal and practical cases of these different integration schemes are simulated and compared to assess whether interconnect structures using a low-k (k = 2.3) dielectric are more suitable than AG interconnects at scaled dimensions. The effect of using an additional (SiC-based) stiff liner on the AG capacitance benefit is also investigated. Finally, we verify our simulations using sub-40 nm half pitch AG structures prepared using the conformal and non-conformal processes.
    Microelectronic Engineering 01/2013; DOI:10.1016/j.mee.2013.12.004 · 1.34 Impact Factor
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    ABSTRACT: The method “trap spectroscopy by charge injection and sensing” (TSCIS) is applied to porous SiOCH low-k dielectrics integrated in MIS capacitors with Ta based diffusion barriers. Most of the low-k samples show an unexpected negative flatband voltage shift with charge injection, which we attribute to positive charge built up in the bulk low-k due to Ta penetration. The only porous low-k sample that can be fitted using the standard TSCIS method is a k=2.0 material in combination with a low pore penetration barrier. The fitted trap distribution demonstrates a low trap density and an amorphous structure. It is also shown that UV treatment can change the low-k charge trapping behavior.
    Reliability Physics Symposium (IRPS), 2013 IEEE International; 01/2013
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    ABSTRACT: The dielectric breakdown field (EBD) and the time-dependent-dielectric-breakdown (TDDB) of eight different low-K films with porosities between 3% (K=3.2) and 50% (K=1.8) and thicknesses between 15 and 60 nm were investigated using imec's planar capacitors (p-cap) test vehicle. EBD values decrease linearly with porosity to reach 6MV/cm at 50% porosity. The analogous Organo-Silicate Glass (OSG) films show a similar field acceleration factors independently of porosity. An OSG 2.0 film with 45% porosity and a periodic mesoporous organosilica (PMO) 1.8 film, both sealed with 12-nm OSG 3.0 sealing also showed the same field acceleration factor. On the other hand, the corresponding Weibull slopes vary and decrease linearly with porosity, which is in agreement with the percolation model. Also, the Weibull slopes decrease linearly with dielectric thickness. Extrapolating those data and analyzing the maximum allowed electrical fields to meet 10-years lifetime (EMAX), critical dielectric spacing are discussed as a function of porosity. It is shown that for 20-nm spacing remedial measures are required for porosities >30%.
    Reliability Physics Symposium (IRPS), 2013 IEEE International; 01/2013
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    ABSTRACT: The residual stresses generated during different processing steps and during thermal cycling of 3D stack packages, mimicking its service life, are quantified by Finite Element Modeling (FEM) together with measurements of dedicated FET arrays used as CPI sensors. Thermo-mechanical deformation of the package can be directly transferred to the Cu/low-k interconnect, inducing large local stresses to drive interfacial crack formation and propagation. The test vehicle used in this work is an imec's proprietary logic CMOS IC on top of which a commercial DRAM is stacked. Different test structures contained in the chip, allow monitoring thermo-mechanical stresses and electrical characteristics of TSV's and micro-bumps. It is shown that FET current shifts can be used to measure the stress in the surface of the chip. The use of standard FEM approach is insufficient to simulate the CPI due to the large dimensional difference between the packaging and interconnects structures. Due to size and speed limitations of commercial computers, a 3D thermo mechanical model of a 3D package cannot contain all the details from the package and at the same time simulate the small structures such as metal and dielectric layers in the BEOL. For this reason, multi-scale simulations are the best choice for identifying the critical regions of the package where high stresses and/or delamination failures are expected to occur. We have shown the methodology to follow to study the CPI.
    Electronics Packaging Technology Conference (EPTC); 12/2012
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    ABSTRACT: Due to their large volume and close proximity to devices, the reliability of copper TSV's is a concern, both with respect to mechanical stresses induced by the TSV in the Si and with respect to copper drift into the liner and the Si. This abstract summarizes recent achievements obtained in imec's 3D-reliability work package where above mentioned reliability concerns are evaluated in detail. To study the impact of mechanical stresses induced by the TSV in the Si, the saturation drain currents Id of transistors have been used as stress sensors. The offset of the Id of transistors closer to a TSV with respect to transistors far away from a TSV has been studied, both directly after processing and after thermal storage and thermal shock. It is shown that stresses generated by the TSV in the Si increase after thermal storage above certain temperatures while thermal shock reduces these stresses. The first is attributed to stress relaxation at high temperatures, while the latter is attributed to cracking/delamination at critical interfaces. To study continuity in TSV-barriers, a method, further referred to as dual ramp rate IVctrl, is introduced. The method consists of controlled current-voltage sweeps at different rates. The difference in breakdown fields for different ramp rates allows estimating TDDB (=Time Dependent Dielectric Breakdown) field acceleration parameters. Applying a negative voltage to the TSV (-V) does not allow copper to drift into the liner, while when applying a positive voltage (+V) to the TSV, copper can drift into the liner in case of a defective, non-continuous barrier. Comparing TDDB field acceleration parameters of -V versus +V tests gives insight in barrier properties. In our study, weak reliability is observed in systems where the TSV-barriers are not continuous.
    Physical and Failure Analysis of Integrated Circuits (IPFA); 07/2012