V.S.L. Cheung

The Hong Kong University of Science and Technology, Kowloon, Hong Kong

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Publications (17)27.57 Total impact

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    ABSTRACT: A 1-V WLAN IEEE 802.11a CMOS transceiver integrates all building blocks on a single chip including a transformer-feedback VCO and a stacked divider for the frequency synthesizer and 8-bit IQ ADCs and 8-bit IQ DACs. Fabricated in a 0.18-mum CMOS process and operated at a single 1-V supply, the receiver and the transmitter consume 85.7 mW and 53.2 mW, including the frequency synthesizer, respectively. The total chip area with pads is 12.5 mm<sup>2</sup>.
    IEEE Journal of Solid-State Circuits 10/2007; · 3.06 Impact Factor
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    P.Y. Wu, V.S.-L. Cheung, H.C. Luong
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    ABSTRACT: A 1-V, 8-bit pipelined ADC is realized using multi-phase switched-opamp (SO) technique. A novel loading-free architecture is proposed to reduce the capacitive loading and to improve the speed in low-voltage SO circuits. Employing the proposed loading-free pipelined ADC architecture together with double-sampling technique and a fast-wake-up dual-input-dual-output switchable opamp, the ADC achieves 100-MS/s conversion rate, which to our knowledge is the fastest ADC ever reported at 1-V supply using SO technique, with performance comparable to that of many high-voltage switched-capacitor (SC) ADCs. Implemented in a 0.18-mum CMOS process, the ADC obtains a peak SNR of 45.2 dB, SNDR of 41.5 dB, and SFDR of 52.6 dB. Measured DNL and INL are 0.5 LSB and 1.1 LSB, respectively. The chip dissipates only 30 mW from a 1-V supply
    IEEE Journal of Solid-State Circuits 05/2007; · 3.06 Impact Factor
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    ABSTRACT: A 1V WLAN IEEE 802.11a CMOS transceiver integrates all building blocks on a single chip including a transformer-feedback VCO and a stacked divider for the synthesizer and 8-bit IQ ADCs and 8-bit IQ DACs. Fabricated in a 0.18-mum CMOS process and operated at a single 1-V supply, the receiver and the transmitter consume 85.7mW and 53.2mW, including the frequency synthesizer, respectively. The total chip area with pads is 12.5 mm<sub>2</sub>
    Solid-State Circuits Conference, 2006. ESSCIRC 2006. Proceedings of the 32nd European; 10/2006
  • K.W.H. Ng, V.S.L. Cheung, H.C. Luong
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    ABSTRACT: A fully differential wideband sixth-order switched-capacitor bandpass filter is designed for channel selection in cable TV applications. A modified double-sampling pseudo-two-path technique is proposed to achieve a second-order wideband bandpass filter with a single opamp. Implemented in a standard double-poly four-metal 0.35-μm CMOS process and operated at 176-MHz sampling frequency, the filter achieves a measured center frequency of 44 MHz with a bandwidth of 6.28 MHz and a dynamic range of 58.3 dB at 3% IM3. The filter consumes 92.5mW at a single 3.0-V supply and occupies a chip area of 0.52 mm <sup>2</sup>.
    IEEE Journal of Solid-State Circuits 04/2005; · 3.06 Impact Factor
  • V.S.L. Cheung, H.C. Luong
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    ABSTRACT: A bandpass ΣΔ modulator is demonstrated to operate at a very high sampling rate of 240 MS/s by employing a proposed double-sampling switched-capacitor biquadratic filter architecture, which processes with a fast-settling feature. Implemented in a standard 0.35-μm CMOS process, the modulator achieves a peak SNDR of 72 dB, 55 dB and 52 dB at a bandwidth of 200 kHz, 1 MHz and 1.25 MHz for GSM, Bluetooth and CDMA2000 applications respectively while dissipating 37 mW and occupying a chip area of 1.2 mm<sup>2</sup>.
    VLSI Circuits, 2004. Digest of Technical Papers. 2004 Symposium on; 07/2004
  • J.M.C. Wong, V.S.L. Cheung, H.C. Luong
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    ABSTRACT: A 1-V low-power high-speed dynamic-loading frequency divider is proposed using novel D flip-flops with a common-gate topology and with a single clock phase. A simple and accurate small-signal analysis model is provided to estimate the operating frequencies of the divider. Implemented in a standard digital 0.35-μm CMOS process and at 1-V supply, the proposed frequency divider measures a maximum operating frequency up to 5.2 GHz with a power consumption of 2.5 mW.
    IEEE Journal of Solid-State Circuits 11/2003; · 3.06 Impact Factor
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    V.S.L. Cheung, H.C. Luong
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    ABSTRACT: A CMOS Bluetooth receiver is implemented using a single conversion low-IF architecture. A low IF of 600 kHz is employed to minimize the power dissipation in the quadrature IF circuitry, which employs switched-opamp technique to guarantee for 1V operation. Realized in a 0.35μm CMOS process ( V<sub>TN</sub> = 0.6 V, V<sub>TP</sub>= -0.77 V) and a single 1V supply, the proposed Bluetooth receiver achieves a measured IIP3 of -18dBm, an image rejection of 28 dB, a noise figure of 29 dB and a sensitivity of -70 dBm while consuming a low power dissipation of 10mW.
    Solid-State Circuits Conference, 2003. ESSCIRC '03. Proceedings of the 29th European; 10/2003
  • V.S.-L. Cheung, H.C. Luong, M. Chan, Wing-Hung Ki
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    ABSTRACT: A 1-V switched-capacitor (SC) quadrature IF circuitry for Bluetooth receivers is demonstrated using switched-opamp technique. To achieve double power efficiency while maintaining low sensitivity to finite opamp gain effects for the SC IF circuitry, half-delay integrator-based filters and ΣΔ modulator have been proposed. The proposed quadrature IF circuitry employs a seventh-order IF filter for channel selection and a third-order ΣΔ modulator for analog-to-digital conversion. A noise-shaping extension technique is employed to enhance the resolution of the low-pass ΣΔ modulator by 16 dB while operating at the same oversampling ratio and power consumption. At a 1-V supply, the quadrature IF circuitry achieves a measured IIP3 of -3 dBm at a nominal gain of 24 dB with a 48-dB variable gain control while consuming a total power dissipation of 3.5 mW.
    IEEE Journal of Solid-State Circuits 06/2003; · 3.06 Impact Factor
  • V.S.L. Cheung, H.C. Luong
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    ABSTRACT: A 0.5 μW switched-capacitor signal-conditioning system with integrated switched-op-amp filter and ΣΔ modulator is implemented in a 0.35 μm CMOS process. A power-efficient single op-amp architecture employing half-delay SC integrators is utilized for the whole system. Operated from a 0.9 V supply, the system has a dynamic range of 45 dB.
    Solid-State Circuits Conference, 2003. Digest of Technical Papers. ISSCC. 2003 IEEE International; 02/2003
  • V.S.L. Cheung, H.C. Luong, Wing-Hung Ki
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    ABSTRACT: A 1 V switched-capacitor (SC) bandpass sigma-delta (ΣΔ) modulator is realized using a high-speed switched-opamp (SO) technique with a sampling frequency of up to 50 MHz, which is improved ten times more than prior 1 V SO designs and comparable to the performance of the state-of-the-art SC circuits that operate at much higher supply voltages. On the system level, a fast-settling double-sampling SC biquadratic filter architecture is proposed to achieve high-speed operation. A low-voltage double-sampling finite-gain-compensation technique is employed to realize a high-resolution ΣΔ modulator using only low-DC-gain opamps to maximize the speed and to reduce power dissipation. On the circuit level, a fast-switching methodology is proposed for the design of the switchable opamps to achieve a switching frequency up to 50 MHz. Implemented in a 0.35-μm CMOS process (V<sub>TP</sub>=0.82 V and V<sub>TN</sub>=0.65 V) and at 1 V supply, the modulator achieves a measured peak signal-to-noise-and-distortion ratio (SNDR) of 42.3 dB at 10.7 MHz with a signal bandwidth of 200 kHz, while dissipating 12 mW and occupying a chip area of 1.3 mm<sup>2</sup>.
    IEEE Journal of Solid-State Circuits 11/2002; · 3.06 Impact Factor
  • V.S.L. Cheung, H.C. Luong, Wing-Hung Ki
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    ABSTRACT: Based on only half-delay switched-capacitor integrators, a 7<sup>th</sup>-order IF-filter and a 3<sup>rd</sup>-order ΣΔ modulator using a novel noise-shaping extension technique are implemented for a Bluetooth receiver in a 0.35-μm CMOS process. At a 1-V supply, the quadrature IF circuitry achieves a measured IIP3 of -3 dBm at a nominal gain of 24 dB through a 48-dB variable-gain control with a power dissipation of 3.5 mW.
    VLSI Circuits Digest of Technical Papers, 2002. Symposium on; 02/2002 · 3.06 Impact Factor
  • V.S.L. Cheung, H. Luong, Mansun Chan
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    ABSTRACT: A 3<sup>rd</sup>-order lowpass ΣΔ modulator operating with a 0.9-V supply voltage is realized with a standard 0.35-μm CMOS process. To achieve ultra-low-power and tiny-chip-area design, single-opamp-based ΣΔ modulator architecture is proposed and implemented with switched-opamp technique. Employing a novel opamp design with three switching output pairs, the ΣΔ modulator achieves a SNR of 75dB at an ultra low power consumption of 0.2μW, which is more than an order lower than existing designs.
    Circuits and Systems, 2002. ISCAS 2002. IEEE International Symposium on; 02/2002
  • J.M.C. Wong, V.S.L. Cheung, H.C. Luong
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    ABSTRACT: A 1-V high-speed dynamic frequency divider using a common-gate topology is proposed. A simple and accurate small-signal analysis model is provided to estimate the operating frequencies. Implemented in a standard 0.35-μm digital CMOS process and at 1-V supply, the proposed frequency divider measures an operating frequency up to 5.2 GHz at a power consumption of 2.5 mW.
    VLSI Circuits Digest of Technical Papers, 2002. Symposium on; 02/2002 · 3.06 Impact Factor
  • K.W.H. Ng, V.S.L. Cheung, H. Luong
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    ABSTRACT: A fully-differential sixth-order switched-capacitor bandpass filter is designed with a 44-MHz center frequency and a bandwidth of 6-MHz for digital video application in a standard 0.35-μm CMOS technology (V<sub>tn</sub> = 0.6 V, V<sub>tp</sub> = -0.8 V). With a modified double-sampling pseudo-two-path technique, the filter achieves a sampling frequency of 176 MHz and consumes 85.5 mW.
    Circuits and Systems, 2002. ISCAS 2002. IEEE International Symposium on; 02/2002
  • V.S.-L. Cheung, H.C. Luong, Wing-Hung Ki
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    ABSTRACT: A modified switched-opamp technique is proposed to enable switched-capacitor (SC) circuits to operate at 1 V with the opamp fully functional in all phases. A 1-V fully differential two-switchable-output-pair operational amplifier has been designed for the proposed technique, which is then employed in a 1-V fully differential SC pseudo-2-path filter. Implemented in a standard single-poly triple-metal 0.5-μm CMOS process, the filter achieves a sixth-order bandpass response centered at 75 kHz with a quality factor of 45. Capacitors formed with polysilicon and highly doped n-well (cap-well option) regions are used to achieve both good linearity and small chip area. At 1-V supply, the filter obtains an output swing of 1.2 V<sub>pp</sub> and a dynamic range of 51 db while dissipating 310 μW and occupying a chip area of 0.8 mm<sup>2</sup>
    IEEE Journal of Solid-State Circuits 02/2001; · 3.06 Impact Factor
  • V.S.L. Cheung, H.C. Luong, W.H. Ki
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    ABSTRACT: A 1 V 10.7 MHz switched-opamp bandpass ΣΔ modulator uses modified double-sampling finite-gain-compensation. In a standard 0.35 μm CMOS process at 1 V supply, the modulator achieves 42.8 MHz effective sampling frequency with 42.3 dB peak SNDR while dissipating 12 mW in 1.3 mm<sup>2</sup> chip area
    Solid-State Circuits Conference, 2001. Digest of Technical Papers. ISSCC. 2001 IEEE International; 02/2001
  • V. Cheung, H. Luong, Wing-Hung Ki
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    ABSTRACT: Switched-opamp (SO) techniques are explored to operate switched capacitor (SC) circuits in 1 V supply without on-chip voltage multiplier or low V<sub>T</sub> devices. However, the existing SO techniques require isolating the opamp from the signal path by turning off completely either the entire opamp or its output stages after the integration phase. As a result, these SO techniques cannot be applied to realize the useful SC pseudo-N-path filters, which require an idle phase in the system for further signal processing. A modified SO technique implements an additional switchable opamp in parallel with the original switchable opamp but working in an alternative clock phase. As such, for every clock phase, there exists an opamp that is fully functional in the SC system. With the two switchable opamps both realized in a two-stage approach, it is sufficient to turn off only the output stages to isolate the signal path. The two switchable opamps are further combined to realize a single two-switchable-output-pair opamp to save power and area and to minimize the mismatch. To demonstrate the idea, a 1 V fully differential two-switchable-output-pair opamp is realized in a 0.5 μm CMOS process with nMOS and nMOS threshold voltages 0.66 V and ~0.85 V respectively
    Solid-State Circuits Conference, 2000. Digest of Technical Papers. ISSCC. 2000 IEEE International; 02/2000

Publication Stats

231 Citations
27.57 Total Impact Points

Institutions

  • 2000–2007
    • The Hong Kong University of Science and Technology
      • Department of Electronic and Computer Engineering
      Kowloon, Hong Kong