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M. Vinet,
T. Poiroux,
C. Licitra,
J. Widiez,
J. Bhandari,
B. Previtali,
C. Vizioz,
D. Lafond,
C. Arvet, P. Besson,
L. Baud,
Y. Morand,
M. Rivoire,
F. Nemouchi,
V. Carron,
S. Deleonibus
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ABSTRACT: In this letter, we report the fabrication and characterization of self-aligned double-gate MOSFETs with gate length down to 6 nm. Based on molecular bonding, the interest of this original process relies on the fact that, for the first time, technological options such as planar process, independently biasable gates, and metallic source and drain are integrated all together to address critical issues for sub-22-nm node, such as variability, short channel effect control, and access resistance decrease. Good electrical performance of pMOS transistors is demonstrated. Short channel effects are very well controlled down to 30 nm. The independent biasing of the two gates allows tuning of the characteristics, depending on the targeted applications.
IEEE Electron Device Letters 08/2009; · 2.85 Impact Factor
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F. Andrieu,
O. Faynot,
X. Garros,
D. Lafond,
C. Buj-Dufournet,
L. Tosti,
S. Minoret,
V. Vidal,
J.C. Barbe,
F. Allain, [......],
B. Guillaumot,
J.P. Colonna, P. Besson,
L. Brevard,
D. Mariolle,
P. Holliger,
A. Vandooren,
C. Fenouillet-Beranger,
F. Martin,
S. Deleonibus
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ABSTRACT: This paper compares, for the first time, the scalability of physical- and chemical-vapor-deposited (PVD and CVD) TiN on HfO<sub>2 </sub> as a gate stack for FDSOI cMOSFETs down to 25nm gate length and width. It is shown that not only the intrinsic material properties but also the device architecture strongly influences the final gate stack properties. Reliability issues, stress and gate control in the sub-35nm scale are reported and explained, thanks to material, electric data and mechanical simulations. In spite of its lower performance on large device dimensions, PVD-TiN demonstrates a better overall trade-off, leading to a 17% ion improvement on 25nm short and narrow devices
Electron Devices Meeting, 2006. IEDM '06. International; 01/2007
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A. Mondot,
M. Muller,
A. Talbot,
C. Vizioz,
S. Pokrant,
F. Leverd,
F. Martin,
C. Leroux,
Y. Morand,
S. Descombes,
D. Aime,
F. Allian, P. Besson,
T. Skotnicki
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ABSTRACT: In this paper, we demonstrate for the first time a new original approach of the integration of dual phase totally silicided (TOSI) gates using a close-to-standard CMOS flow without any additional CMP step targeting the use of NiSi for NMOS and Ni<sub>2</sub>Si for the PMOS gate electrode on high-k dielectrics. The impact of the TOSI-process on the gate stack characteristics is investigated in detail on capacitance, gate leakage and work function data. With respect to poly-Si gated devices we find a significant reduction of the effective oxide thickness in inversion without degradation of the gate leakage statistics. The results emphasize the potential of the integration of TOSI-gates on high-k gate oxides
Solid-State Device Research Conference, 2006. ESSDERC 2006. Proceeding of the 36th European; 10/2006
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ABSTRACT: Photoemission spectroscopy using synchrotron radiation was used to determine the band offsets, as a function of depth, of ultrathin (3.5 nm) Hf-silicate grown by chemical vapor deposition onto SiO2/Si and nitrided at 750 and 700 °C using NH3. In agreement with recent studies on the nitridation of oxides, the nitridation raises the valence-band (VB) maximum by adding N 2p states in the band gap. VB offsets of 1.6–1.9 eV are measured after nitridation. Final state screening in the gate oxide and band-bending at the SiO2/Si interface must be included in order to deduce accurate band offsets.
Applied Physics Letters 04/2006; 88(16):162906-162906-3. · 3.84 Impact Factor
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A. Mondot,
M. Muller,
D. Aime,
B. Froment,
F. Cacho,
A. Talbot,
F. Leverd,
M. Rivoire,
Y. Morand,
S. Descombes, P. Besson,
A. Toffoli,
S. Pokrant,
T. Skotnicki
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ABSTRACT: In this paper, we present a detailed analysis of the performance and transport characteristics in totally Ni silicided (TOSI) devices. For two different TOSI integration schemes, we study transconductance variations of TOSI devices with respect to poly-Si gated devices. We find a clear signature of process induced strain related to the total gate silicidation step which depends largely on the integration scheme used for the fabrication of the TOSI devices.
Solid-State Device Research Conference, 2005. ESSDERC 2005. Proceedings of 35th European; 10/2005
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M. Vinet,
T. Poiroux,
J. Widiez,
J. Lolivier,
B. Previtali,
C. Vizioz,
B. Guillaumot,
Y. Le Tiec, P. Besson,
B. Biasse,
F. Allain,
M. Casse,
D. Lafond,
J.-M. Hartmann,
Y. Morand,
J. Chiaroni,
S. Deleonibus
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ABSTRACT: Thanks to bonding, metal-gate etching without any out-of-gate Si consumption, and self-aligned transfer of alignment marks, we have processed the first 10-nm-gate-length DG MOS transistors with metal gates. These devices exhibit excellent short-channel effects control and high-performance characteristics. Their saturation current is very sensitive to the access resistance increase caused by film thinning required to respect the scaling rules. Moreover, their electrical properties can be tuned between LSTP and HP by independently biasing the two gates.
IEEE Electron Device Letters 06/2005; · 2.85 Impact Factor
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O. Weber,
F. Ducroquet,
T. Ernst,
F. Andrieu,
J.-F. Damlencourt,
J.-M. Hartmann,
B. Guillaumot,
A.-M. Papon,
H. Dansas,
L. Brevard,
A. Toffoli, P. Besson,
F. Martin,
Y. Morand,
S. Deleonibus
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ABSTRACT: For the first time, MOS transistors with compressively strained SiGe(:C) channel, metal gate and high-k dielectric are demonstrated down to 55nm gate length. SiGe(:C) surface channel pMOSFETs with HfO<sub>2</sub> gate dielectric exhibit a 10<sup>4</sup> gate leakage reduction and a 65% mobility enhancement at high transverse effective field (1MV/cm) when compared to the universal SiO<sub>2</sub>/Si reference. With such a thin Equivalent Oxide Thickness (EOT= 16-18Å), this represents the best gate leakage/mobility trade-off ever published.
VLSI Technology, 2004. Digest of Technical Papers. 2004 Symposium on; 07/2004
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ABSTRACT: X-ray photoelectron spectroscopy using synchrotron radiation has been used to investigate the HfO2/SiO2 interface chemistry of high-quality 0.6 and 2.5 nm HfO2/0.6 nm SiO2/Si structures. The high energy resolution (0.15 eV) along with the high brightness level allows us to separate, unambiguously, on both Hf 4f and Si 2p core-level spectra, interfacial Hf–silicate bonds from bulk HfO2 and SiO2 contributions, thus making possible subsequent quantitative treatments and modeling of the interfacial layer structure. Careful assessment of the energy shift of the interfacial components shows that Si-rich Hf silicates are present. The underlying assumption that initial-state contribution dominates the observed Si 2p shift is briefly discussed. © 2002 American Institute of Physics.
Applied Physics Letters 11/2002; 81(19):3627-3629. · 3.84 Impact Factor
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A. Fernandes,
B. DeSalvo,
T. Baron,
J.F. Damlencourt,
A.M. Papon,
D. Lafond,
D. Mariolle,
B. Guillaumot, P. Besson,
P. Masson,
G. Ghibaudo,
G. Panankakis,
F. Martin,
S. Haukka
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ABSTRACT: Presents electrical and physical characteristics of memory devices
with high density Si quantum dots integrated on SiO<sub>2</sub>/ALD Al
<sub>2</sub>O<sub>3</sub> tunnelling dielectrics. Devices show high
threshold voltage shift at low programming voltages and good reliability
behaviour. ALD Al<sub>2</sub>O<sub>3</sub> can be ascribed as a suitable
surface for well-controlled growth of crystalline Si quantum dots for
future memory applications
Electron Devices Meeting, 2001. IEDM Technical Digest. International; 02/2001
