[Show abstract][Hide abstract] ABSTRACT: We present for the first time Gate-Last (GL) planar Fully Depleted (FD) SOI MOSFETs featuring both ultra thin silicon body (3-5 nm) and BOX (25 nm). Transistors with metal-last on high-k first (TiN/HfSiON) have been successfully fabricated down to 15nm gate length. We have thoroughly characterized the gate stack (reliability, work-function tuning on Equivalent Oxide Thickness EOT=0.85nm) and transport (hole mobility, Raccess) for different surface and channel orientations. We report excellent ION, p=1020μA/μm at IOFF, p=100nA/μm at VDD=0.9V supply voltage for <;110> pMOS channel on (001) surface with in-situ boron doped SiGe Raised Source and Drain (RSD) and compressive CESL. This is explained by the high efficiency of the strain transfer into the ultra-thin channel, as evidenced by physical strain measurements (dark field holography).
[Show abstract][Hide abstract] ABSTRACT: We integrated planar fully depleted (FD) SOI MOSFETs with a gate-last on high-k first (GL-HKF) down to gate lengths of Lg = 15 nm and active widths of W = 80 nm. Such an integration scheme enables reaching for pMOSFETs a threshold voltage of VTp = −0.2 V and one decade gate current (JG) gain, as well as similar hole mobility and ON-currents, compared to pMOSFETs integrated with a gate first. This approach is also benchmarked with high-k last (GL-HKL) stacks in terms of leakage, equivalent oxide thickness (EOT), effective work-function (EWF) and flat band voltage (VFB) shift under stress.
[Show abstract][Hide abstract] ABSTRACT: This paper presents the prototype of a 3D circuit with Wide I/O interconnects in a 65nm CMOS node, assembled in a face-to-back integration and reported on a BGA. The process technology carried out for the realization of the bottom die will be presented in both 200mm and 300mm environment. Finally, the 3D assembly will be successfully assessed through electrical and reliability tests, concretising the realism of a 3D technology for future Wide I/O products.
[Show abstract][Hide abstract] ABSTRACT: We study the effective metal gate work function (WF<sub>Meff</sub>) of different metal/high-κ gate stacks. Both capacitance versus voltage measurement and internal photo emission measurement were used, leading to a better understanding of the WF<sub>Meff</sub> variations. We demonstrate that these variations are related to two main process dependent parameters, a voltage drop at the high- κ/SiO<sub>2</sub> interface and the metal work function. These two parameters are studied for various process conditions.
IEEE Transactions on Electron Devices 09/2010; · 2.36 Impact Factor
[Show abstract][Hide abstract] ABSTRACT: Ruthenium is promoted as one of the most efficient metallization contact material in MEMS technology. In a good agreement with MEMS technology requirement, a cost friendly chemical mixture based on sodium hypochlorite is proposed hereafter to achieve a robust and reliable ruthenium wet etching process through a resist mask in a 200mm single wafer spray tool.
[Show abstract][Hide abstract] ABSTRACT: Thanks to relaxed pattern dimensions and friendly wet process cost, MEMS technology uses a great number of wet etch process steps during process flow. Nevertheless, as dimensions are downscaling, for the very used gold wet etch process, a limited under etch of the gold layer under photo resist mask is required. This paper makes a comparison between a gold wet etch process in immersion mode and a gold wet etch process with a single wafer spray tool.
[Show abstract][Hide abstract] ABSTRACT: In this letter, we report the fabrication and characterization of self-aligned double-gate MOSFETs with gate length down to 6 nm. Based on molecular bonding, the interest of this original process relies on the fact that, for the first time, technological options such as planar process, independently biasable gates, and metallic source and drain are integrated all together to address critical issues for sub-22-nm node, such as variability, short channel effect control, and access resistance decrease. Good electrical performance of pMOS transistors is demonstrated. Short channel effects are very well controlled down to 30 nm. The independent biasing of the two gates allows tuning of the characteristics, depending on the targeted applications.
IEEE Electron Device Letters 08/2009; · 3.02 Impact Factor
[Show abstract][Hide abstract] ABSTRACT: Combining two different electrical characterisation methods on the same MOS capacitors, we demonstrate that the flat band voltage of High-κ metal gate stack is determined by a dipole at the High-κ/SiO2 interface. Meanwhile, roll-off of flat band voltage, occurring for thin SiO2 inter layer, is also associated to a dipole variation at this same interface. We have measured its value and we show that this dipole is highly influenced by the High-κ material in contact with the SiO2. Moreover, we also demonstrate its strong dependence on the process conditions. Finally, for a same metal gate and depending on the High-κ in contact with SiO2, we show that this dipole can induce up to 1.7eV variation in the gate effective work function. However, controlling the dipole magnitude remains a strong issue especially for the thinnest EOT.
[Show abstract][Hide abstract] ABSTRACT: New reactants such as ozone dissolved in ultra-pure water have been widely used the last few years instead of the original Radio Corporation of America (RCA) cleaning (which is a combination of the Standard Cleaning 1 (SC1) and the Standard Cleaning 2 (SC2)). In a first part of the study (Microelectron. Eng. 83 (2006) 1986), we had quantified the efficiency of a new cleaning sequence (that calls upon HF and H2O/O3 solutions) on polished Si1−xGex virtual substrates (x = 0.2–0.5). We are discussing here the surface morphology and wetability together with the oxide thickness and structure typically obtained after this so-called “DDC-SiGe” wet cleaning. Flat surface morphologies are found after cleaning whatever the Ge content (from 20 to 50%). Typical root mean square roughness is around 0.4 nm. We have used X-ray Photoelectron Spectroscopy to determine the characteristics of the surface termination after this “DDC-SiGe” cleaning. An oxide mainly composed of SiO2 is formed, with a low fraction of Ge sub-oxide and GeO2. The distribution of chemical species is not that different from the one obtained after the use of a SC1 cleaning. However, the chemical oxide formed is slightly thicker. Such a HF/O3 cleaning leads, when used on thick Ge layers grown on Si, to the formation of a really thin Ge sub-oxide. Our oxidation model assumes a competition in O3 solutions between the oxidation rates of Si and Ge atoms (faster for Si) and the dissolution of the Ge oxide formed in solution. This mechanism, which implies the formation of a slightly porous oxide, is different from the one seeming to occur in SC1-based solutions. Indeed, the addition of surfactant in a SC1 solution modifies the oxidation rate compared to standard SC1 or O3-based solutions, suggesting a diffusion of reactants towards the interface between the SiGe and the oxide in formation, assisted by the reactions of species within the cleaning solutions.
[Show abstract][Hide abstract] ABSTRACT: This paper investigates the impact of crystallinity of HfO<sub>2</sub> oxides on V<sub>T</sub> instabilities. Wet etch rate measurements enhances a critical thickness t<sub>HK</sub> <sup>C</sup> for HfO<sub>2</sub> which marks the transition between a monoclinic crystalline phase to a near amorphous state, both clearly identified by ATR FTIR. Using electrical measurements and modeling, it is demonstrated that this transition from the crystalline phase to an amorphous state is accompanied by a strong reduction of the density of bulk HfO<sub>2</sub> defects responsible for electron trapping, Prevents the crystallization of an high-k layer is therefore fundamental to improve its BTI reliability.
[Show abstract][Hide abstract] ABSTRACT: In this paper, we extract the gate work function of metal/High-K stacks (WF<sub>M</sub>) with an internal photoemission (IPE) based method and a C(V) characterization method. We attempt to apply both of them on the same specially designed samples. We show that it leads to a better reliability of WF<sub>M</sub> and highlights new phenomena.
Solid State Device Research Conference, 2007. ESSDERC 2007. 37th European; 10/2007
[Show abstract][Hide abstract] ABSTRACT: Focus has been made on the so-called "Leti BKM-Clean" advanced surface preparation, developed on a 300 mm single wafer spin-on platform. Based on the "Dilute Dynamic Clean" (DDC) knowledge , dilute HF/HCl and O3/HCl chemistries have been investigated here in combined spin-on and immersion mode. Depending on the specific FEOL cleaning step requirements, the HF/HCl step can be tuned in order to precisely control the partial or total silicon surface de-oxidation as for pre-gate cleanings which require a controlled chemical oxide re-growth. In this last case, the Leti BKM-Clean presents good particle performance up to 65 nm particles size, good particle and metallic removal efficiency without any feature damage generation on high-K /TiN/poly-Si lines structures with an aspect ratio lower than 4.
[Show abstract][Hide abstract] ABSTRACT: The paper deals with the nickel selective etching chemistries with respect to NiGe and high Ge content NiSiGe layers. Chemistries depicted in the literature are discussed. A focus is put on H2SO4 96% ("water free" approach), for which the etching mechanism is investigated.
[Show abstract][Hide abstract] ABSTRACT: In this work we evaluate the impact of the gate stack layers deposition technologies and their combination on the thermal stability of the stack with respect to EOT vs leakage figure of merit. Two HfO2 deposition technologies have been used: ALCVD and AVD (for Atomic Vapor Deposition); and two TiN deposition technologies have been evaluated: CVD and PVD. As a result, it appears that stack stability after a 1050 °C spike anneal can be achieved by combination of AVD HfO2 and PVD TiN. Anyway a trade-off in terms of mobility degradation using this metallic layer deposition technique is still present.