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ABSTRACT: This paper presents an ultra-wideband (UWB) low noise amplifier (LNA) consuming 2.2-mW core dc power for 6-8.5GHz wireless applications. A common-gate input stage is cascaded with a common-source second stage to perform input impedance matching and wideband stagger-tuning amplification, while the current-reuse topology minimizes the dc power dissipation. The design method used to achieve flat-gain response is presented. A detailed analysis gives insight into the issue on the input impedance and suggests a solution. Implemented in a 90-nm CMOS process, the measurement results show power gain of 13.35+/-0.55 dB, input third intercept point (IIP3) of-6.2 dBm, and noise figure of 5-6.5 dB. The silicon die with 0.22-mm<sup>2</sup> active area allows the design to be adopted for highly integrated low-cost CMOS applications.
Circuits and Systems (ISCAS), Proceedings of 2010 IEEE International Symposium on; 07/2010
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ABSTRACT: Operation in the subthreshold region most often is synonymous to minimum-energy operation. Yet, the penalty in performance is huge. In this paper, we explore how design in the moderate inversion region helps to recover some of that lost performance, while staying quite close to the minimum-energy point. An energy-delay modeling framework that extends over the weak, moderate, and strong inversion regions is developed. The impact of activity and design parameters such as supply voltage and transistor sizing on the energy and performance in this operational region is derived. The quantitative benefits of operating in near-threshold region are established using some simple examples. The paper shows that a 20% increase in energy from the minimum-energy point gives back ten times in performance. Based on these observations, a pass-transistor based logic family that excels in this operational region is introduced. The logic family operates most of its logic in the above-threshold mode (using low-threshold transistors), yet containing leakage to only those in subthreshold. Operation below minimum-energy point of CMOS is demonstrated. In leakage-dominated ultralow-power designs, time-multiplexing will be shown to yield not only area, but also energy reduction due to lower leakage. Finally, the paper demonstrates the use of ultralow-power design techniques in chip synthesis.
Proceedings of the IEEE 03/2010; · 6.81 Impact Factor
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ABSTRACT: The explosive growth in the density of wirelessly connected devices and their traffic load is creating interference and gradually leading to a severe spectrum shortage. Approaches to address this challenge include dynamic spectrum allocation (cognitive radio) and pro-active interference mitigation strategies requiring coordination between heterogeneous networking technologies. This paper describes a modular and scalable methodology and architecture, called Connectivity Brokerage, that enables proactive co-existence and collaboration between diverse technologies, making joint optimization of the scarce spectrum resources possible.
Radio and Wireless Symposium (RWS), 2010 IEEE; 02/2010
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ABSTRACT: This paper presents the design and implementation of a low-energy asynchronous logic topology using sense amplifier-based pass transistor logic (SAPTL). The SAPTL structure can realize very low energy computation by using low-leakage pass transistor networks at low supply voltages. The introduction of asynchronous operation in SAPTL further improves energy-delay performance without a significant increase in hardware complexity. We show two different self-timed approaches: 1) the bundled data and 2) the dual-rail handshaking protocol. The proposed self-timed SAPTL architectures provide robust and efficient asynchronous computation using a glitch-free protocol to avoid possible dynamic timing hazards. Simulation and measurement results show that the self-timed SAPTL with dual-rail protocol exhibits energy-delay characteristics better than synchronous and bundled data self-timed approaches in 90-nm CMOS.
IEEE Transactions on Very Large Scale Integration (VLSI) Systems 08/2009; · 1.22 Impact Factor
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ABSTRACT: Along with changing technologies and design techniques, target applications span a wide range: from large-scale computing to personal services and perceptual interfaces. The authors of this article characterize these workloads of the future and argue for a new set of benchmarks to guide the exploration and optimization of future systems.
IEEE Design and Test of Computers 08/2008; 25(4):358-365. · 1.39 Impact Factor
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ABSTRACT: A power interface IC is designed and demonstrated to convert and manage power for a wireless tire pressure sensor node. The IC includes two switched-capacitor DC-DC converters to supply power to the various components of the sensor at their appropriate voltages. The design of the two integrated converters is discussed, including the optimization of capacitors and power transistors. The losses due to parasitic capacitances are analyzed. Two gate drive techniques are used to drive the gates of the floating triple-well transistors. A synchronous rectifier efficiently harvests energy from an electromagnetic shaker and control circuitry regulates the output voltage while minimizing power consumption. The two converters achieve efficiencies of approximately 84% while the synchronous rectifier achieves an efficiency of 88%.
Power Electronics Specialists Conference, 2008. PESC 2008. IEEE; 07/2008
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ABSTRACT: The design of an MB-OFDM ultra-wideband receiver is challenging when we target power consumption minimization while providing enough robustness against the nearby wireless interference. We present an optimized receiver front-end design obtained by a systematic design space exploration technique based on the platform-based design (PBD) methodology. At the system level, we investigate the interference effects and propose an approach to estimate the inter-modulation products introduced by receiver nonlinearities. We show how we map the system-level performance requirements to circuit-level platforms through an optimization process. We obtain a RF front-end consuming 10.8 mW in a 0.13 mum CMOS technology, which achieves a 22.3% savings of power compared to a manually optimized design.
Circuits and Systems for Communications, 2008. ICCSC 2008. 4th IEEE International Conference on; 06/2008
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ABSTRACT: This paper presents the design and implementation of a low energy asynchronous logic architecture using sense amplifier-based pass transistor logic (SAPTL). The SAPTL structure can realize very low energy computation by using low leakage pass transistors and low supply voltage. The introduction of asynchronous operation in SAPTL further improves energy-delay performance and reliability without increasing hardware complexity. We show two different self-timed approaches using a bundled-data and a dual-rail handshaking protocol, respectively. The proposed self-timed SAPTL architectures provide robust and efficient asynchronous computation using a glitch-free protocol to avoid possible dynamic timing hazards. Simulation results show that the self-timed SAPTL with dual-rail protocol exhibits energy-delay characteristics better than synchronous and bundled-data self-timed approaches.
Asynchronous Circuits and Systems, 2008. ASYNC '08. 14th IEEE International Symposium on; 05/2008
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J.M. Rabaey
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ABSTRACT: Summary form only given. The wireless communications field has experienced a truly amazing growth since the early 1990's. Wireless connectivity slowly but surely has become pervasive. One would expect that by now this revolution must be losing some steam, but the truth is far from that. If anything, it is gathering even more speed. In the coming decades, introduction of innovative wireless technologies will enable a broad range of exciting applications to come to fruition, and reshape the way we interact with our daily living environment. Underlying it all is a three-tiered environment consisting of a large number of huge data and compute centers, billions of mobile compute and computation devices, and potentially trillions of tiny sensors and actuators. Making this happen will require some important wireless roadblocks to be either overcome or circumvented. A short list of those includes spectrum scarcity, reliability, complexity, security and obviously power. In this presentation, a number of innovative and even revolutionary solutions to address these will be discussed. Examples are collaborative cognitive networks, wireless in the mm-wave region of the spectrum, and miniature wireless. Each of these approaches pushes some part of the design technology to its limits, and may even require a totally novel approach towards design, all this while semiconductor technology is trying to cope with the uncertainty of design in the nanometer regime. One thing is for sure - the wireless designer of the next decade is bound for some very exciting times.
Design Automation Conference, 2008. ASPDAC 2008. Asia and South Pacific; 04/2008
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ABSTRACT: A wake-up receiver (WuRx) is used in wireless sensor networks (WSN) to detect wireless traffic directed to a node's receiver and activate it upon detection, improving network latency and energy dissipation by maximizing data transceiver sleep time. The always-on nature of the WuRx sets a power dissipation floor for the entire system. In realistic WSN scenarios, the adoption of a WuRx leads to energy savings only if it can be realized with about 50muW of power dissipation in Lin, E.Y., et al, (2004), testing the limits of low-power receiver design. While diode detectors provide for the simplest detector structure, such receivers are strongly gain-limited due to the thresholding effect of the nonlinear detector in Pletcher, N., et al, (2007) and adding gain at RF to improve sensitivity only increases power consumption. A more attractive approach is to adopt a heterodyne architecture, where the extra gain needed for robust energy detection can be obtained at an intermediate frequency (IF) with a much lower power cost. However, a survey of previous receiver designs for WSN reveals that the power requirements of the required local oscillator (LO) exceed the total power budget of the WuRx in Otis, B., et al, (2005).
Solid-State Circuits Conference, 2008. ISSCC 2008. Digest of Technical Papers. IEEE International; 03/2008
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ABSTRACT: A power interface IC is designed and demonstrated to convert and manage power for a wireless tire pressure sensor node. Power conversion is performed using on-chip switched-capacitor converters with size-optimized devices and level-shifting gate drivers. A synchronous rectifier efficiently harvests energy from an electromagnetic shaker and control circuitry regulates the output voltage while minimizing power consumption. The converters achieve efficiencies approaching 80%.
Custom Integrated Circuits Conference, 2007. CICC '07. IEEE; 10/2007
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ABSTRACT: Summary form only given. The availability of wireless transceivers transmitting over ranges from few microns to less than half a meter opens the door for a wide range of exciting new applications, ranging from seamless system assembly, smart surfaces, healthcare monitoring and intelligent machinery and components. However, the implementation challenges in terms of size and power for most of these applications are pushing the limits. Fortunately, by exploring the wide range of options offered to the designer, extremely small and virtually zero-power transceivers are feasible. This paper discusses the opportunities, challenges and options of short distance wireless, and illustrates the proposed techniques with several design examples. In addition, the challenges that emerge when trying to embed these nodes into very dense networks are explored. Special consideration is given to the issues of distributed synchronization, localization and robust communication.
Digital System Design Architectures, Methods and Tools, 2007. DSD 2007. 10th Euromicro Conference on; 09/2007
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ABSTRACT: This paper presents the principles for designing low-power transmitters for wireless sensor networks. Based on these principles, an injection-locked transmitter is implemented in a standard 0.13-mum CMOS process and packaged using chip-on-board assembly. The transmitter utilizes a film bulk acoustic resonator (FBAR) to obtain a stable carrier at 1.9 GHz. At 0 dBm output power, the transmitter achieves an efficiency of 32% at 50 kb/s and 28% at 156 kb/s. With 50% on-off keying, the transmitter consumes 1.6 and 1.8 mW, respectively
IEEE Journal of Solid-State Circuits 09/2006; · 3.23 Impact Factor
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ABSTRACT: With semiconductor technology feature size scaling below 100 nm, mixed-signal design faces some important challenges, caused among others by reduced supply voltages, process variation, and declining intrinsic device gains. Addressing these challenges requires innovative solutions, at the technology, circuit, architecture, and design-methodology level. We present some of these solutions, including a structured platform-based design methodology to enable a meaningful exploration of the broad design space and to classify potential solutions in terms of the relevant metrics.
Proceedings of the IEEE 07/2006; · 6.81 Impact Factor
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ABSTRACT: We present the design methodology and a silicon implementation of a baseband system for use in wireless sensor network applications. Starting from the RF interface, our design process began with a system level phase inspired by the platform-based design (PBD) methodology extended to the analog domain. The functional design was based on an early-late gate synchronization scheme. The PBD approach was used to explore two alternative solutions: a predominantly digital one and a predominantly analog one. To validate the functional aspect of the design, a prototype implementation based on an FPGA and a field programmable analog array (FPAA) was derived using the PBD approach. Finally, we mapped the system level description to silicon aiming at an ultra low power implementation exploiting weak inversion in a 0.13μCMOS process leading to an overall power consumption of 200μW with a 1V supply.
Custom Integrated Circuits Conference, 2005. Proceedings of the IEEE 2005; 10/2005
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ABSTRACT: A 1.9GHz CMOS digitally controlled oscillator (DCO) is designed in a standard 0.13μm process, targeting ultra low power frequency synthesizers for wireless sensor network transceivers. The oscillator exploits subthreshold device operation and a low 0.5V supply to achieve power consumption of only 100μW. A novel switched capacitor configuration is employed to realize a frequency resolution of 200 kHz with a tuning range of 150MHz. High quality bondwire inductors also reduce power consumption. The phase noise is -114dBc/Hz at 1MHz offset, achieving performance competitive with other published work.
Solid-State Circuits Conference, 2005. ESSCIRC 2005. Proceedings of the 31st European; 10/2005
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ABSTRACT: In this paper, a detailed study of the performance of geographic routing protocols in the presence of localization errors is carried out. Both analytical and simulation results illustrate the major impact or localization errors on the protocol goodput and route discovery energy. The performance metrics observed were the packet delivery ratio and the power consumed at a node for routing. It is shown that significant performance deterioration occurs with location errors as low as 20% of a node's radio range with no other obstacles in the network. To counteract this degradation, an enhancement is proposed that increases the error tolerance to about 40% radio range and in addition improves the performance consistently for any location error. Furthermore, the effect of obstacles in conjunction with location errors on the routing performance is also investigated.
Communications, 2005. ICC 2005. 2005 IEEE International Conference on; 06/2005
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ABSTRACT: The common belief is that a multi-hop configuration with rather small per-hop distance is the only viable energy-efficient option for wireless sensor networks. We discuss a single hop configuration, utilizing the asymmetry between lightweight sensor nodes and a more powerful "base station" and demonstrate that such a single hop configuration can actually have lower overall power consumption than a multi-hop counterpart.
Wireless Communications and Networking Conference, 2005 IEEE; 04/2005
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ABSTRACT: Different opportunistic routing protocols have been proposed recently for routing in sensor networks. These protocols exploit the redundancy among nodes by using a node that is available for routing at the time of packet transmission. This mitigates the effect of varying channel conditions and duty cycling of nodes that make static selection of routes not viable. However, there is a downside as each hop may provide extremely small progress towards the destination or the signaling overhead for selecting the forwarding node may be too large. In this paper, we provide a systematic performance evaluation, taking into account different node densities, channel qualities and traffic rates to identify the cases when opportunistic routing makes sense. The metrics we use are power consumption at the nodes, average delay suffered by packets and goodput of the protocol. Our baseline for comparison is geographic routing with nodes being duty cycled to conserve energy. The paper also identifies optimal operation points for opportunistic routing that minimizes the power consumption at nodes.
Pervasive Computing and Communications Workshops, 2005. PerCom 2005 Workshops. Third IEEE International Conference on; 04/2005
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ABSTRACT: Scaling of silicon integrated technology into the deep sub-100 nm space brings with it a number of formidable challenges to the designer. Issues such as design complexity, power dissipation, process variability and reliability are challenging the traditional design methodologies. In this presentation, it is conjectured that the only viable long-term solution to these challenges is to drastically revise the way we do design, and a road map of potential solutions is presented. Ultimately, these innovative design solutions will help to pave the way to the post-silicon era.
Design Automation Conference, 2005. Proceedings of the ASP-DAC 2005. Asia and South Pacific; 02/2005
