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ABSTRACT: Summary form only given. Memory reliability is a key issue of flash technology. The continuous trend to increase the storage density is driving the technology close to its physical limits and new reliability challenges are met. The tutorial discussed the failure mechanisms limiting memory endurance and data retention. Reference was made to the two mainstream flash technologies, considering a floating-gate cell in a NOR- or NAND-type memory array. The first part of the tutorial was dedicated to failure modes related to the intrinsic cell behavior. Classical data loss mechanisms and the degradation of the oxide properties caused by high-field tunneling or channel hot electron injection were examined. The second part dealt with single-cell failures, in particular low-temperature data loss after program/erase cycling, which can be ascribed to tunnel oxide defects. The nature of the leakage current and its relation with the stress-induced leakage current observed in large area capacitors was discussed. Design solutions to solve, or at least ease, this issue was considered.
Integrated Reliability Workshop Final Report, 2005 IEEE International; 11/2005
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ABSTRACT: In this paper we report the most important progresses on flash memory reliability in the last decade. The capability of mastering the degradation mechanisms, mainly related to the generation of localized defects in the tunnel oxide during writing operations, comes from the large know-how developed in more that 20 years of research and industrial activity.
Electron Devices Meeting, 2004. IEDM Technical Digest. IEEE International; 01/2005
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ABSTRACT: With reference to the mainstream technology, the most relevant failure mechanisms that affect reliability of Flash memory are reviewed, showing the primary role played by tunnel oxide defects. The degradation of device. performance induced by program/erase cycling is discussed, specifically for what concern the leakage that affect a very small fraction of memory cells after cycling. The dependence of the leakage on tunnel oxide thickness, number of cycles, and temperature is analyzed. The leakage current is explained by trap-assisted tunneling involving one, two or more traps, with decreasing occurrence probability. Finally, data are presented showing the robustness of scaled Flash memory to alpha particles and electromagnetic radiation.
Integrated Circuit Design and Technology, 2004. ICICDT '04. International Conference on; 02/2004
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ABSTRACT: This paper mainly focuses on the development of the NOR flash memory technology, with the aim of describing both the basic functionality of the memory cell used so far and the main cell architecture consolidated today. The NOR cell is basically a floating-gate MOS transistor, programmed by channel hot electron and erased by Fowler-Nordheim tunneling. The main reliability issues, such as charge retention and endurance, are discussed, together with an understanding of the basic physical mechanisms responsible. Most of these considerations are also valid for the NAND cell, since it is based on the same concept of floating-gate MOS transistor. Furthermore, an insight into the multilevel approach, where two bits are stored in the same cell, is presented. In fact, the exploitation of the multilevel approach at each technology node allows an increase of the memory efficiency, almost doubling the density at the same chip size, enlarging the application range and reducing the cost per bit. Finally, NOR flash cell scaling issues are covered, pointing out the main challenges. Flash cell scaling has been demonstrated to be really possible and to be able to follow Moore's law down to the 130-nm technology generations. Technology development and consolidated know-how is expected to sustain the scaling trend down to 90- and 65-nm technology nodes. One of the crucial issues to be solved to allow cell scaling below the 65-nm node is the tunnel oxide thickness reduction, as tunnel thinning is limited by intrinsic and extrinsic mechanisms.
Proceedings of the IEEE 05/2003; · 6.81 Impact Factor
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G. Campardo,
R. Micheloni,
S. Commodaro,
E. Yero,
M. Zammattio,
S. Mognoni,
A. Sacco,
M. Picca,
A. Manstretta,
M. Scotti,
I. Motta,
C. Golla,
A. Pierin,
R. Bez,
A. Grossi,
A. Modelli, A. Visconti,
O. Khouri,
G. Torelli
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ABSTRACT: This paper presents a 3-V-only 64-Mb 4-level-cell (2-b/cell)
NOR-type channel-hot-electron (CHE) programmed flash memory fabricated
in 0.18-μm shallow-trench isolation CMOS technology. The device (die
size 40 mm<sup>2</sup>) is organized in 64 1-Mb sectors. Hierarchical
column and row decoding ensures complete isolation between different
sectors during any operation, thereby increasing device reliability
while still providing layout area optimization. Staircase gate-voltage
programming is used to achieve narrow threshold-voltage distributions.
The same program throughput as for bilevel CHE-programmed memories is
obtained, thanks to parallel programming. A mixed balanced/unbalanced
sensing approach allows efficient use of the available threshold window.
Asynchronous (130-ns access time) and burst-mode (up to 50-MHz data
rate) reading is possible. Both column and row redundancy is provided to
ensure extended failure coverage. Error correction code techniques,
correcting 1 failed over 32 data cells, are also integrated
IEEE Journal of Solid-State Circuits 12/2000; · 3.23 Impact Factor
