Abdollah Khoei

Urmia University, Rezâiyye, Āz̄ārbāyjān-e Gharbī, Iran

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Publications (134)32.63 Total impact

  • [Show abstract] [Hide abstract]
    ABSTRACT: In this paper, an ultrafast steady-state genetic algorithm processor (GAP) is presented. Due to the heavy computational load of genetic algorithms (GAs), they usually take a long time to find optimum solutions. Hardware implementation is a significant approach to overcome the problem by speeding up the GAs procedure. Hence, we designed a digital CMOS implementation of GA in 0.18 μm process. The proposed processor is not bounded to a specific application. Indeed, it is a general-purpose processor, which is capable of performing optimization in any possible application. Utilizing speed-boosting techniques, such as pipeline scheme, parallel coarse-grained processing, parallel fitness computation, parallel selection of parents, dual-population scheme, and support for pipelined fitness computation, the proposed processor significantly reduces the processing time. Furthermore, by relying on a built-in discard operator the proposed hardware may be used in constrained problems that are very common in control applications. In the proposed design, a large search space is achievable through the bit string length extension of individuals in the genetic population by connecting the 32-bit GAPs. In addition, the proposed processor supports parallel processing, in which the GAs procedure can be run on several connected processors simultaneously.
    07/2015; DOI:10.1109/TCYB.2015.2451595
  • Sarang Kazeminia · Khayrollah Hadidi · Abdollah Khoei
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    ABSTRACT: A straightforward methodology of optimizing ring-oscillator phase-locked loops (PLLs) is organized for integer-N PLLs. Then, a brief 4-step design flow is concluded to implicitly quantize the loop components for optimized loop stability. Theoretical analysis confirms that the ratio of more than 20 is required for loop filter's capacitors to yield at least 65° degrees phase margin. A wide-range voltage controlled oscillator (VCO) is proposed which is continuously controlled through two fast and slow response paths. The fast-response path improves RMS jitter due to decreasing loop delay and the slower one is an adaptive bias tuning loop, utilized to reduce the power consumption at lower operating frequencies. The RMS jitter of around 2 ps and 0.35 ps at 250 MHz and 4 GHz operating frequencies are obtained, respectively, where the 1.8 V supply voltage is subjected to about 60 mV peak-to-peak noise and reference clock suffers from 12 ps peak-to-peak jitter. Power consumption is reduced from 12.6-4 mW at 250 MHz operating frequency when the adaptive bias scheme is applied. Furthermore, Simulation results confirm 35% and 50% improvement in RMS and peak-to-peak jitter at 250 MHz operating frequency, respectively, when the ratio of capacitances is increased from 10 to 20 within the loop filter. The proposed PLL can be implemented in 170 μm × 250 μm active area in 0.18 μm CMOS process.
    Journal of Circuits System and Computers 05/2015; 24(07):1550104. DOI:10.1142/S0218126615501042 · 0.33 Impact Factor
  • Amir Fathi · Abdollah Khoei · Khayrollah Hadidi
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    ABSTRACT: This paper describes the design of a high speed min/max architecture based on a new current comparator. The main advantage of the proposed circuit which employs a novel preamplifier-latch comparator is the higher operating frequency feature in comparison with previous works. Because the comparator can work in voltage mode, the min/max structure can be redesigned either in voltage or current mode. The designed comparator is refreshed without any external clock. Therefore, it does not degrade the speed performance of proposed min/max structure. These features along with low power consumption qualify the proposed architecture to be widely used in high speed fuzzy logic controllers (FLCs). Post-layout simulation results confirm 3.4 GS/s comparison rate with 9-bit resolution for a 0.9 V peak-to-peak input signal range for the comparator and 800 MHz operating frequency for min/max circuit. The power consumption of whole structure is 912 mu W from a 1.8 V power supply using TSMC 0.18-mu m CMOS technology.
    Journal of Circuits System and Computers 04/2015; 24(04):1550048. DOI:10.1142/S0218126615500486 · 0.33 Impact Factor
  • S Yuvarajan · Abdollah Khoei
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    ABSTRACT: The paper describes a novel PWM scheme called inverted-sine PWM (ISPWM) which uses a sinusoidal reference and an inverted-sine carrier. The ISPWM, when applied to a rectifier, has a better harmonic elimination and a higher average output voltage compared to a sine PWM (SPWM). The harmonic content of the ISPWM output for different values of the modulation index is computed and compared with that of a SPWM. The complete circuit for generating the ISPWM control signal for single and three phase ac-dc converters is developed. Experimental waveforms of voltages and currents are presented.
    IETE Journal of Research 03/2015; 48(2):85-92. DOI:10.1080/03772063.2002.11416261 · 0.19 Impact Factor
  • Abdollah Khoei · Khayrollah Hadidi · Bayan Nasri
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    ABSTRACT: This paper presents design of a digital fuzzy logic controller IC based on Active-rule-driven architecture. Different ideas have been used in inference and defuzzification stages to obtain high processing speed. This produces a parallel processing mechanism from fuzzification to defuzzification. The controller was designed by 0.35 μm CMOS technology and the layout design was obtained by MAGIC software which has 892274 μm2 size. The circuits were simulated using HSPICE software. The resulting speed for processing was 50 MHz (25 MFLIPS).
    IETE Journal of Research 03/2015; 51(6):447-457. DOI:10.1080/03772063.2005.11416425 · 0.19 Impact Factor
  • A Khoei · Kh Hadidi · S Jamal · S Yuvarajan
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    ABSTRACT: The development of a PC-based fuzzy controller for controlling the speed of a dc motor is considered. It is shown that the proposed controller results in a reduced chattering around the set point as compared to a basic fuzzy controller. The performance of the fuzzy controller and its capability of optimizing the parameters like maximum overshoot and rise time are described. The results obtained on a practical dc motor control system are presented.
    IETE Journal of Research 03/2015; 48(2):93-98. DOI:10.1080/03772063.2002.11416262 · 0.19 Impact Factor
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    ABSTRACT: An open loop voltage buffer with an exact unity gain using a positive local feedback technique with a conventional source follower is proposed. Stability of the buffer is determined by evaluating the location of the poles and zeros and its linearity is studied using Volterra series expansion. The proposed buffer is laid out in 0.35-μm standard CMOS technology. Post layout simulations demonstrate that the buffer gain is close to unity with less than 0.2% error. The power consumption is 10 mw from a 3.3 V power supply and the achieved total harmonic distortion is -78 dB for a 10 MHz input frequency. Also Monte-Carlo simulations are carried out to investigate effects of random mismatches on the circuit operation.
    Journal of Circuits System and Computers 02/2015; 24(4):1550058. DOI:10.1142/S0218126615500589 · 0.33 Impact Factor
  • Source
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    ABSTRACT: A novel topology for a high gain two-stage amplifier is proposed. The proposed circuit is designed in a way that the non-dominant pole is at output of the first stage. A positive capacitive feedback (PCF) around the second stage introduces a left half plane (LHP) zero which cancels the phase shift introduced by the non-dominant pole, considerably. The dominant pole is at the output node which means that increasing the load capacitance has minimal effect on stability. Moreover, a simple and effective method is proposed to enhance slew rate. Simulation shows that slew rate is improved by a factor of 2.44 using the proposed method. The proposed amplifier is designed in a 0.18um CMOS process. It consumes 0.86mW power from a 1.8V power supply and occupies 3038.5um2 of chip area. The DC gain is 82.7dB and gain bandwidth (GBW) is 88.9 MHz when driving a 5pF capacitive load. Also low frequency CMRR and PSRR+ are 127dB and 83.2dB, respectively. They are 24.8dB and 24.2dB at GBW frequency, which are relatively high and are other important properties of the proposed amplifier. Moreover, Simulations show convenient performance of the circuit in process corners and also presence of mismatch.
    IET Circuits Devices & Systems 11/2014; 9(3). DOI:10.1049/iet-cds.2014.0139 · 0.91 Impact Factor
  • Naser Beyraghi · Abdollah Khoei
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    ABSTRACT: In this paper, a novel current-mode Four-quadrant analog multiplier is proposed. The newly designed current squarer circuits and one current mirror which all operate in low supply voltage (2 V) are the basic building blocks in realization of the mathematical equations. The multiplier circuit is designed by using 0.35 μm standard CMOS technology and to validate the circuit performance, the proposed multiplier has been simulated in HSPICE simulator. The simulation results demonstrate a linearity error of 0.17%, a THD of 0.16% in 1 MHz, a −3 dB bandwidth of 485 MHz and a maximum power consumption of 0.232 mW while the static power consumption is 0.111 mW.
    AEU - International Journal of Electronics and Communications 10/2014; 69(1). DOI:10.1016/j.aeue.2014.10.015 · 0.55 Impact Factor
  • Source
    Sarang Kazeminia · Khayrollah Hadidi · Abdollah Khoei
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    ABSTRACT: In this paper, a 16-phases 20MHz to 110MHz low jitter delay locked loop, DLL, is proposed in a 0.35μm CMOS process. A sensitive open loop phase detector, PD, is introduced based on a novel idea to simply detect small phase differences between reference clock and generated delayed signals. High sensitivity, besides the simplicity reduces the dead zone of PD and gives a better jitter on output generated clock signals, consequently. A new strategy of common mode setting is utilized on differential delay elements which no longer introduce extra parasitics on output nodes and brings the duty cycle of generated clock signals near to 50 percent. Also, small amplitude differential clock is carefully transferred inside the circuit to considerably suppress the noise effect of supply voltage. Post-Layout simulation results confirm the RMS jitter of less than 6.7ps at 20MHz and 2ps at 100MHz input clock frequency when the 3.3Volts supply voltage is subject to 75mVolts peak-to-peak noise disturbances. Total power consumption reaches from 7.5mW to 16.5mW when the operating frequency increases from 20MHz to 100MHz. The proposed low-jitter DLL can be implemented in small active area, around 380μm×210μm including the clock generation circuit, which is proper to be repeatedly used inside the chip.
  • Naser Beyraghi · Abdollah Khoei · Khayrollah Hadidi
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    ABSTRACT: In this paper a CMOS current-mode analog multiplier circuit based on a novel current-mode squarer circuit is proposed. The circuit is simulated using HSPICE simulator and designed in 0.35 A mu m standard CMOS technology with +/- A 1.5 V supply voltage. The simulation results of proposed multiplier for input current range of +/- 10 mu A demonstrate a -3 dB bandwidth of 24.5 MHz, 475 mu W as maximum power consumption, nonlinearity of 1.3 % and a THD of 0.87 % at 1 MHz.
    Analog Integrated Circuits and Signal Processing 07/2014; 80(3). DOI:10.1007/s10470-014-0367-0 · 0.40 Impact Factor
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    ABSTRACT: This article is attributed to a novel 4-2 compressor based on a new structure with a special feature of having no glitch at the output waveform. Speed enhancement is achieved through the quick production of Cout and optimum tuning of the width of utilizing transistors. The delay of the proposed structure is about 130ps in which the authenticity of our claim is proved by using the results extracted by Hspice software using CSMC 0.18μm technology.
    2014 MIXDES - 21st International Conference "Mixed Design of Integrated Circuits & Systems"; 06/2014
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    ABSTRACT: What is discussed in this article is a current mode membership function generator (MFG) which consists of digital and analog parts or in other words it is a mixed mode MFG. The proposed MFG which consumes less power and perform in high speed can generate output shapes(S, Z, triangular and trapezoidal) and by exploiting 7 switches, slope and height altering and also horizontal shifting is available. The simulation results are performed in Hspice (level 49) under CMOS 0.18μm technology.
    2014 MIXDES - 21st International Conference "Mixed Design of Integrated Circuits & Systems"; 06/2014
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    ABSTRACT: This article discusses about a fuzzy controller. The fuzzifier is designed with a novel structure which is more suitable than other topologies and it has a high accuracy and speed. The processing unit, inference engine, is extracted out of reference [1] that is able to generate both maximum and minimum of its inputs currents simultaneously. Ultimately, the defuzzifier is simple and the center of area (COA) is used in this section. The simulation results are performed in Hspice (level 49) under CMOS 0.18μm technology. The inference speed of this controller (with two inputs, one output and sixteen rules) is about 42.6 MFLIPS.
    2014 MIXDES - 21st International Conference "Mixed Design of Integrated Circuits & Systems"; 06/2014
  • Sarang Kazeminia · Khayrollah Hadidi · Abdollah Khoei
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    ABSTRACT: This article presents a low-jitter wide-range, 250MHz to 4GHz, PLL based on a fast responding VCO. The proposed VCO is controlled through two fast and slow response paths on oscillating elements. In fast section the control voltage of VCO is directly applied to a device to bypass extra current of differential pair tail device. Hence, the loop response to fast fluctuations of control voltage is speeded up and reduces the RMS jitter. An adaptive bias tuning scheme, as the slow response loop, effectively prevents passing a large bypass current from the sink device at lower operating frequencies and reduces the power consumption. The proposed PLL limits the RMS jitter to about 2ps and 300fs at 200MHz and 4GHz operating frequencies, respectively, where the 1.8v supply voltage is subjected to a peak-to-peak noise voltage of about 60mv and an input clock jitter of about 12ps. Power consumption is reduced to 4mW from otherwise 12.6mW at 200MHz operating frequency by using the proposed adaptive bias scheme. Power consumption increases to 9mW at 4GHz for 1.8v power supply voltage. The proposed PLL's area is 170μm×250μm in a 0.18μm CMOS process.
    22nd Iranian Conference on Electrical Engineering (ICEE); 05/2014
  • Sarang Kazeminia · Khayrollah Hadidi · Abdollah Khoei
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    ABSTRACT: The closed loop structure of ring-oscillator based integer-N PLLs, to achieve a desired phase margin, is thoroughly analyzed. Furthermore, a straightforward design methodology is implicitly introduced. The analysis proves that the ratio of the large capacitance to the small one, for a 65 degrees phase margin, in the loop filter of integer-N PLLs, should be at least 20 rather than 7 to 10, which is commonly practiced based on some widely read literatures, [6]. There are works, however, which have used greater capacitance ratios, 13, 20 and 32, without providing a theoretical base. Also, enhancing phase margin to 70 and 80 degrees requires capacitance ratios of 31 and 130, respectively. It is also proved that the maximum phase margin is achieved when the unity gain bandwidth, ωu, is adjusted at the geometrical median frequency of the zero and the third pole. Simulation results confirm 35% and 50% improvement in RMS and peak to peak jitter at 250MHz operating frequency, respectively, when the ratio of capacitances is modified from 10 to 20.
    22nd Iranian Conference on Electrical Engineering (ICEE); 05/2014
  • Sarang Kazeminia · Khayrollah Hadidi · Abdollah Khoei
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    ABSTRACT: A 10-bit pipeline analog-to-digital converter is presented with the ability of converting small input peak-to-peak voltages of around 100mvolts. Two-Stage comparators in flash structure are cautiously scheduled for both pre-amplification and latch operations, applying a simple switching strategy to reduce the coupling noise effect of transferring digital signals into analog sections. Namely, the digital signal which is used to schedule pre-amplification and latch operations is shared for all comparators such that be transferred out of the analog section in geometrical floorplanning. The first stage is also modified to reduce kickback noise effect of latch stage on analog inputs. Simulation results confirm the SNDR and SFDR of around 60.9dB and 71.5dB for 1.5MHz input frequency at 32MS/s sampling rate, respectively, when the peak-to-peak of input signal is 100mvolts. These values are reduced to 59.9dB and 70.6dB at near nyquist input frequency, around 15.5MHz. Also, at 50MS/s sampling rate, SNDR and SFDR are obtained around 57dB and 66.6dB at near nyquist input frequency of 24.2MHz.
    22nd Iranian Conference on Electrical Engineering (ICEE), Iran; 05/2014
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    ABSTRACT: A 13-bit analog-to-digital converter (ADC) is designed in 0.35 μm CMOS technology that reduces the power consumption through sharing the resources between pipeline stages. Using a dummy sample-and-hold (S/H) and recirculating concept the requirements for the first stage are relaxed and the design restrictions are resolved. This ADC does not use a dedicated S/H and reaches a speed of 50 MS/s. The design is tested with TSMC mixed-signal 0.35 μm technology and post layout simulations shows over 75 dB Signal-to-Noise and Distortion-Ratio (SNDR) and over 85 dB Spurious Free Dynamic Range (SFDR) at the Nyquist frequency. The designed chip occupies an area of 1.3 mm–0.7 mm and consumes 164 mW power at Nyquist from a 3.3 V supply.
    Journal of Circuits System and Computers 05/2014; 23(06). DOI:10.1142/S021812661450090X · 0.33 Impact Factor
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    ABSTRACT: A very simple, wide range and programmable pulse width controller or duty cycle corrector (DCC) is presented. Simulating the circuit in 0.35 μm Complementary MOSFET (CMOS) technology shows that the frequency range of the input signal can be within 250 MHz to 1.6 GHz, with a duty cycle of 30–70%. The proposed circuit generates an output signal with programmable duty cycle in the range of 30–70% with steps of 10% which could be extended to more steps by simple variations. The systematic peak-to-peak jitter at center frequency (1 GHz) is 1ps, while adding a random noise source of 5% of the power supply, increases it to 13 ps. the power consumption at maximum speed (1.6 GHz) is 4.9 mW. Monte Carlo simulations show maximum of 3.4% error at the 1.5 GHz input frequency and 70% output duty cycle.
    Journal of Circuits System and Computers 05/2014; 23(05). DOI:10.1142/S0218126614500753 · 0.33 Impact Factor
  • Source
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    ABSTRACT: A high-speed and high-accuracy continuous-time common-mode feedback block (CMFB) is presented. To satisfy speed and accuracy requirements, some modifications have been applied on differential difference amplifier (DDA) CMFB circuit. The proposed method is applied to a folded cascode op-amp with power supply of 3.3 V. In order to verify the proposed circuit, simulations are done in 0.35 μm standard CMOS technology. In the worst condition when the output common-mode (CM) voltage is initialized to VCC or GND, only 1.1 ns is required to set the output CM voltage on the desired level. Also in a wide range of input CM voltage variations, the deviation of the output CM voltage from reference voltage is less than 6 mV, so simulation results confirm the expected accuracy and speed while simultaneously the proposed CMFB circuit preserves other characteristics of DDA CMFB circuit such as unity gain frequency, 3-dB bandwidth, phase margin and linearity.
    Journal of Circuits System and Computers 05/2014; 23(05). DOI:10.1142/S0218126614500650 · 0.33 Impact Factor

Publication Stats

359 Citations
32.63 Total Impact Points

Institutions

  • 1996–2015
    • Urmia University
      • • Microelectronics Research Center
      • • Department of Electrical Engineering
      • • Group of Electronic Egineering
      Rezâiyye, Āz̄ārbāyjān-e Gharbī, Iran