Abdollah Khoei

Urmia University, Rezâiyye, Āz̄ārbāyjān-e Gharbī, Iran

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Publications (121)21.54 Total impact

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    ABSTRACT: A novel topology for a high gain two-stage amplifier is proposed. The proposed circuit is designed in a way that the non-dominant pole is at output of the first stage. A positive capacitive feedback (PCF) around the second stage introduces a left half plane (LHP) zero which cancels the phase shift introduced by the non-dominant pole, considerably. The dominant pole is at the output node which means that increasing the load capacitance has minimal effect on stability. Moreover, a simple and effective method is proposed to enhance slew rate. Simulation shows that slew rate is improved by a factor of 2.44 using the proposed method. The proposed amplifier is designed in a 0.18um CMOS process. It consumes 0.86mW power from a 1.8V power supply and occupies 3038.5um2 of chip area. The DC gain is 82.7dB and gain bandwidth (GBW) is 88.9 MHz when driving a 5pF capacitive load. Also low frequency CMRR and PSRR+ are 127dB and 83.2dB, respectively. They are 24.8dB and 24.2dB at GBW frequency, which are relatively high and are other important properties of the proposed amplifier. Moreover, Simulations show convenient performance of the circuit in process corners and also presence of mismatch.
    11/2014;
  • Naser Beyraghi, Abdollah Khoei
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    ABSTRACT: In this paper, a novel current-mode Four-quadrant analog multiplier is proposed. The newly designed current squarer circuits and one current mirror which all operate in low supply voltage (2 V) are the basic building blocks in realization of the mathematical equations. The multiplier circuit is designed by using 0.35 μm standard CMOS technology and to validate the circuit performance, the proposed multiplier has been simulated in HSPICE simulator. The simulation results demonstrate a linearity error of 0.17%, a THD of 0.16% in 1 MHz, a −3 dB bandwidth of 485 MHz and a maximum power consumption of 0.232 mW while the static power consumption is 0.111 mW.
    AEU - International Journal of Electronics and Communications 10/2014; · 0.55 Impact Factor
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    ABSTRACT: In this paper, a 16-phases 20MHz to 110MHz low jitter delay locked loop, DLL, is proposed in a 0.35μm CMOS process. A sensitive open loop phase detector, PD, is introduced based on a novel idea to simply detect small phase differences between reference clock and generated delayed signals. High sensitivity, besides the simplicity reduces the dead zone of PD and gives a better jitter on output generated clock signals, consequently. A new strategy of common mode setting is utilized on differential delay elements which no longer introduce extra parasitics on output nodes and brings the duty cycle of generated clock signals near to 50 percent. Also, small amplitude differential clock is carefully transferred inside the circuit to considerably suppress the noise effect of supply voltage. Post-Layout simulation results confirm the RMS jitter of less than 6.7ps at 20MHz and 2ps at 100MHz input clock frequency when the 3.3Volts supply voltage is subject to 75mVolts peak-to-peak noise disturbances. Total power consumption reaches from 7.5mW to 16.5mW when the operating frequency increases from 20MHz to 100MHz. The proposed low-jitter DLL can be implemented in small active area, around 380μm×210μm including the clock generation circuit, which is proper to be repeatedly used inside the chip.
    Journal of Information Systems and Telecommunication. 09/2014; 2(3):166-172.
  • Analog Integrated Circuits and Signal Processing 07/2014; · 0.55 Impact Factor
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    ABSTRACT: This article discusses about a fuzzy controller. The fuzzifier is designed with a novel structure which is more suitable than other topologies and it has a high accuracy and speed. The processing unit, inference engine, is extracted out of reference [1] that is able to generate both maximum and minimum of its inputs currents simultaneously. Ultimately, the defuzzifier is simple and the center of area (COA) is used in this section. The simulation results are performed in Hspice (level 49) under CMOS 0.18μm technology. The inference speed of this controller (with two inputs, one output and sixteen rules) is about 42.6 MFLIPS.
    2014 MIXDES - 21st International Conference "Mixed Design of Integrated Circuits & Systems"; 06/2014
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    ABSTRACT: This article is attributed to a novel 4-2 compressor based on a new structure with a special feature of having no glitch at the output waveform. Speed enhancement is achieved through the quick production of Cout and optimum tuning of the width of utilizing transistors. The delay of the proposed structure is about 130ps in which the authenticity of our claim is proved by using the results extracted by Hspice software using CSMC 0.18μm technology.
    2014 MIXDES - 21st International Conference "Mixed Design of Integrated Circuits & Systems"; 06/2014
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    ABSTRACT: A 13-bit analog-to-digital converter (ADC) is designed in 0.35 μm CMOS technology that reduces the power consumption through sharing the resources between pipeline stages. Using a dummy sample-and-hold (S/H) and recirculating concept the requirements for the first stage are relaxed and the design restrictions are resolved. This ADC does not use a dedicated S/H and reaches a speed of 50 MS/s. The design is tested with TSMC mixed-signal 0.35 μm technology and post layout simulations shows over 75 dB Signal-to-Noise and Distortion-Ratio (SNDR) and over 85 dB Spurious Free Dynamic Range (SFDR) at the Nyquist frequency. The designed chip occupies an area of 1.3 mm–0.7 mm and consumes 164 mW power at Nyquist from a 3.3 V supply.
    Journal of Circuits System and Computers 05/2014; 23(06). · 0.24 Impact Factor
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    ABSTRACT: A very simple, wide range and programmable pulse width controller or duty cycle corrector (DCC) is presented. Simulating the circuit in 0.35 μm Complementary MOSFET (CMOS) technology shows that the frequency range of the input signal can be within 250 MHz to 1.6 GHz, with a duty cycle of 30–70%. The proposed circuit generates an output signal with programmable duty cycle in the range of 30–70% with steps of 10% which could be extended to more steps by simple variations. The systematic peak-to-peak jitter at center frequency (1 GHz) is 1ps, while adding a random noise source of 5% of the power supply, increases it to 13 ps. the power consumption at maximum speed (1.6 GHz) is 4.9 mW. Monte Carlo simulations show maximum of 3.4% error at the 1.5 GHz input frequency and 70% output duty cycle.
    Journal of Circuits System and Computers 05/2014; 23(05). · 0.24 Impact Factor
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    ABSTRACT: A high-speed and high-accuracy continuous-time common-mode feedback block (CMFB) is presented. To satisfy speed and accuracy requirements, some modifications have been applied on differential difference amplifier (DDA) CMFB circuit. The proposed method is applied to a folded cascode op-amp with power supply of 3.3 V. In order to verify the proposed circuit, simulations are done in 0.35 μm standard CMOS technology. In the worst condition when the output common-mode (CM) voltage is initialized to VCC or GND, only 1.1 ns is required to set the output CM voltage on the desired level. Also in a wide range of input CM voltage variations, the deviation of the output CM voltage from reference voltage is less than 6 mV, so simulation results confirm the expected accuracy and speed while simultaneously the proposed CMFB circuit preserves other characteristics of DDA CMFB circuit such as unity gain frequency, 3-dB bandwidth, phase margin and linearity.
    Journal of Circuits System and Computers 05/2014; 23(05). · 0.24 Impact Factor
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    ABSTRACT: The basic bandgap reference voltage generator, BGR, is thoroughly analyzed and relations are reconstructed considering dependency of bandgap energy, Eg, to absolute temperature. The previous works all consider Eg as a constant, independent of temperature variations. However, Eg varies around 25 meV when the temperature is increased from 2 to 92 °C. In this paper the dependence of Eg to absolute temperature, based on HSPICE mosfet models in HSPICE MOSFET Models Manual (Version X-2005.09, 2005), is approximated by a third-order polynomial using Lagrangian interpolating method within the temperature range of 2–92 °C. Accurate analysis on the simplified polynomial reveals that the TC of VBE must be corrected to −1.72 mV/°K at 27 °C which has been formerly reported about −1.5 mV/°K in Razavi (Design of analog CMOS integrated circuits, 2001) and Colombo et al. (Impact of noise on trim circuits for bandgap voltage references, 2007), −2 mV/°K in Gray et al. (Analysis and design of analog integrated circuits, 2001), Leung and Mok (A sub-1-V 15-ppm/°C CMOS bandgap voltage reference without requiring low threshold voltage device, 2002), Banba et al. (A CMOS bandgap reference circuit with sub-1-V operation, 1999), and −2.2 mV/°K in Jones and Martin (Analog integrated circuit design, 1997), Tham and Nagaraj (A low supply voltage high PSRR voltage reference in CMOS process, 1995). Another important conclusion is that the typical weighting coefficient of TC+ and TC− terms is modified to about 19.84 at 27 °C temperature from otherwise 16.76, when Eg is considered constant, and also 17.2, in widely read literatures, (Razavi in Design of analog CMOS integrated circuits, 2001). Neglecting the temperature dependence of Eg might introduce a relative error of about 20.5 % in TC of VBE. Also, resistance and transistor size ratios, which denote the weighting coefficient of TC+ term, might be encountered to utmost 20.3 % error when the temperature dependence of Eg is ignored.
    Analog Integrated Circuits and Signal Processing 04/2014; 79(1). · 0.55 Impact Factor
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    ABSTRACT: This paper presents a new Fuzzy Logic Controller (FLC) having the ability to support fractional polynomial membership functions. These functions are general form of triangular and trapezoidal membership functions, and also those functions which are used in linguistic hedge FLC (LHFLC). A two-input, single-output Takagi – Sugeno – Kang (TSK) type 0 FLC is designed in 0.35μm standard CMOS process. Analog realization of the circuit makes the design programmable and extendable, while having high speed and low power consumption. Also all the control signals and input signals are in voltage form and no need for digital programmability. Voltage mode realization of the circuits leads to simple use of FLC with other circuits which are in voltage mode like sensors. Simulation results of the controller using Hspice simulator and BSIM3v3 parameters, and comparing them with ideal results obtained from MATLAB software verifies the functionality and performance of the design.
    Fuzzy Sets and Systems 04/2014; · 1.75 Impact Factor
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    ABSTRACT: In this article, an analog fully programmable membership function generator (MFG) is presented. It is capable of generating Gaussian, Triangular and Trapezoidal shapes as well as S or Z shapes. For omitting noise disturbances, differential structures are utilized in input and output stages which are in voltage mode and current mode, respectively. In contrast with conventional MFGs which are controlled digitally or by mixed signal approaches, this structure is a fully programmable analog MFG. It is capable of modifying slope, position and height of output's current. The most distinguishing features of this MFG are its capability of generating ultra-high speed outputs reaching speeds as high as 200 MHz and consuming a very low amount of power. Due to the simple structure of this MFG, it consumes a small active area at the size of 20 μm × 30 μm. It is constructed of only 16 transistors. This MFG has been designed in 0.35 μm CMOS technology. The simulations have been done with Hspice using TSMC, BSIM3 (V3.1) model.
    Journal of Intelligent and Fuzzy Systems 02/2014; · 0.94 Impact Factor
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    ABSTRACT: A new open loop, high resolution CMOS sample and hold (S/H) circuit is introduced in this article. This circuit is constructed based on a new method which leads to a great reduction in dependency of the storing charge of the holding capacitors to the charge injection of transistors. It is a combination of dummy switches and auxiliary capacitors in order to decrease the voltage spikes that are produced during the sampling mode. Due to the high linearity feature of our proposed design in comparison with previous works, it is reached to a great improvement in signal to noise and distortion ratio up to about 15 dB and it’s ENOB is equivalent with about 16 bits. Another advantages of our proposed design are it’s lower power dissipation and it’s high input voltage range. Also the optimum functionality of our proposed circuit does not damaged by the threshold voltage’s variations in different corners. As our proposed S/H circuit has been designed in open loop structure, it is suitable for high speed applications.
    Analog Integrated Circuits and Signal Processing 02/2014; 78(2). · 0.55 Impact Factor
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    ABSTRACT: One of the active areas of fuzzy logic applications is control systems. In this paper presents a proposed Fuzzy Logic Controller FLC chip utilized a novel Membership Function Circuit MFC which can be made programmable. This membership function features of large dynamic range, high current driving, high noise immunity and is simply tunable by setting some voltages on IC pins. Each input of controller has five membership functions and output has seven singletons. A new structure for Min/Max operators, and also, a new current-mode divider circuit with very small area, very low power consumption and high speed and accurate are presented, which are compatible to the proposed MFC, are also given. This controller is a general-purpose two-input one-output fuzzy controller that can be implemented in 0.08-mm2 in 0.35-μm CMOS technology BSIM3v3. For general control tasks, input-output inference of FLC is voltage/voltage. The maximum delay in output of FLC is about 67-ns that correspond to 15-MFLIPS Fuzzy Logic Inference per Second and power consumption is 2.5-mW.
    Journal of Intelligent & Fuzzy Systems: Applications in Engineering and Technology. 01/2014; 26(1):63-76.
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    ABSTRACT: This paper presents a novel structure for implementing rational-powered membership functions (RPMFs), which are the extended forms of triangular/trapezoidal membership functions and those functions which are generated by applying linguistic hedges. The hardware realization of an RPMF consists of a triangular membership function generator circuit followed by a rational-powered generator module (RPGM). A novel fully programmable compact triangular/trapezoidal/s-shaped/z-shaped membership function generator with the ability to continuously change parameters is presented which is compatible with the proposed RPGM. A new method is introduced to implement the RPGM based on the approximation of the function “x a ” by the functions square and square-rooter which are simply implemented in a current-mode analog approach based on the translinear principle, which leads to a design that is simple, and has high accuracy and less hardware usage, with a resulting lower chip area and lower power consumption. The designed circuit was simulated by an HSPICE simulator with level 49 parameters (BSIM3v3), and the simulation results show that the maximum power consumption of the RPGM is 800 μW, while the maximum RMS error is 1.25 %. Finally, layouts of the circuits prepared using Cadence software are presented.
    Circuits Systems and Signal Processing 11/2013; 33(5):1337-1352. · 0.98 Impact Factor
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    ABSTRACT: A 16-phases low jitter delay locked loop, DLL, based on a simple phase detector is proposed in 0.35μm CMOS process. Moreover, a sensitive phase detector is introduced which detects small phase differences of input and generated clock signals. High sensitivity, besides the simplicity reduces the dead zone of the phase detector and yields a better clock jitter, consequently. A new strategy of common mode level setting is proposed for differential delay elements which no longer introduce extra parasitics on output nodes. Also, the input differential clock is carefully transferred inside the chip to considerably reduce the noise effect of power supply. Post-Layout simulation results confirm the RMS jitter of about 6.7ps at 20MHz and 2ps at 100MHz input clock frequency when the 3.3v power supply is subject to 75mv peak-to-peak noise. Total power consumption reaches from 7.5mW to 16.5mW when the operating frequency increases from 20MHz to 100MHz.
    21st Iranian Conference on Electrical Engineering (ICEE); 05/2013
  • A. Mesri, A. Khoei, K. Hadidi
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    ABSTRACT: This paper presents a new current-mode accurate and fully programmable Interval Type-2 (IT2) membership function generator (MFG) in 0.18-μm CMOS technology. This IT2 MFG is based on a Type-1(T1) MFG that uses a new method for slope tuning. The proposed slope tuning method, leads to smaller active area and also significantly smaller total die area by reducing the number of required pins in comparison with previous methods. Small area, low power consumption and especially suitable programming method, makes the proposed IT2 MFG suitable for fuzzifier block of general-purpose Fuzzy Logic Controllers (FLCs). The proposed IT2 MFG has an average power consumption of 800μW and occupies 0.0032mm2. Simulation results using HSPICE for TSMC 0.18μm CMOS technology are presented to analyze the behavior of designed circuits.
    Electrical Engineering (ICEE), 2013 21st Iranian Conference on; 01/2013
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    ABSTRACT: A novel evolutionary algorithm with fixed genetic parameters rate have presented for block-based neural network (BbNN) training. This algorithm can be used in BbNN training which faces complicated problems such as simulation of equations, classification of signals, image processing and implementation of logic gates and so on. The fixed structure of our specific BbNN allows us to implement the trained network by a fixed circuit rather than utilizing a reconfigurable hardware which is usually employed in conventional designs. Avoiding the reconfigurable hardware leads to lower power consumption and chip area. All simulations are performed in MATLAB software.
    Pattern Recognition and Image Analysis (PRIA), 2013 First Iranian Conference on; 01/2013
  • S. Kazeminia, K. Hadidi, A. Khoei
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    ABSTRACT: A 16-phases low jitter delay locked loop, DLL, based on a simple phase detector is proposed in 0.35μm CMOS process. Moreover, a sensitive phase detector is introduced which detects small phase differences of input and generated clock signals. High sensitivity, besides the simplicity reduces the dead zone of the phase detector and yields a better clock jitter, consequently. A new strategy of common mode level setting is proposed for differential delay elements which no longer introduce extra parasitics on output nodes. Also, the input differential clock is carefully transferred inside the chip to considerably reduce the noise effect of power supply. Post-Layout simulation results confirm the RMS jitter of about 6.7ps at 20MHz and 2ps at 100MHz input clock frequency when the 3.3v power supply is subject to 75mv peak-to-peak noise. Total power consumption reaches from 7.5mW to 16.5mW when the operating frequency increases from 20MHz to 100MHz.
    Electrical Engineering (ICEE), 2013 21st Iranian Conference on; 01/2013
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    ABSTRACT: In this paper a novel wideband amplifier based on a positive feedback is presented. The utilizing feedback network includes two capacitors and an emitter degeneration resistor which does not affect the low frequency behavior of the amplifier. Also a series-series mode is exploited to compensate the miller effect of Cμ and to decrease the input capacitance. The proposed method is obtained a 200% gain bandwidth enhancement with respect to a simple differential pair and a 21% improvement considering other topologies in the literature.
    Electrical Engineering (ICEE), 2013 21st Iranian Conference on; 01/2013