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ABSTRACT: A wide-band frequency synthesizer based on time-to-digital (TDC) and digital-to-voltage (DVC) conversion techniques is proposed here. The proposed frequency synthesizer has the capabilities of jitter reduction and large bandwidth, making it more robust for high-frequency applications. A test chip is designed and fabricated in 0.6-μm CMOS single-poly triple-metal process. Here, the novel DVC circuit is realized by tristate inverters, where the resolution can achieve 0.2 mV. Control stability of jitter can improve about 24 dB by exploiting the TDC-based controller. In order to achieve high output frequency and large output range, an analog voltage-controlled oscillator is designed to provide a locked range from 900 to 1900 MHz with <22 kHz resolution at 3.3 V. Simulation and test results show that the proposal can work as expected. Moreover, the TDC-based controller can be treated as soft IP to speed up turnaround time.
IEEE Journal of Solid-State Circuits 11/2002; · 3.23 Impact Factor
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ABSTRACT: With the rapid advance in CMOS technology, the trend of the VLSI
then towards system-on-chip (SOC) where design methodology, cost, and
turnaround time are major issues. Concepts of intellectual property (IP)
are then proposed to fit for SOC designs. Based on a DFS controller IP,
a wideband digital frequency synthesizer (DFS) is proposed to fit in
with the wireless LAN applications, which provides low cost and
efficient design periods. A 2-stage voltage-controlled oscillator (VCO)
is designed to achieve the system requirements and generates such a
high-speed frequency. Its output frequency range can be from 465 MHz to
2.635 GHz with double 3.0-V supplies. Besides, a novel cell-based
digital-to-voltage converter (DVC) is also proposed to solve the
interface between the DFS controller IP and the VCO. The wideband DFS is
fabricated in 0.35-um SPQM CMOS technology
Circuits and Systems, 2001. ISCAS 2001. The 2001 IEEE International Symposium on; 06/2001
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ABSTRACT: A new portable clock generator with full pull-in range and fast
acquisition is presented in this paper, where it can be developed at
hardware description language (HDL) to reduce design cycle as well as
improve system-level integration simulation. In the proposed design,
frequency tracking is performed by the “Prune-and-Search”
algorithm, and the digital-controlled ring oscillator is constructed by
CMOS standard cells. In order to reduce propagation delay of the loop
divider, a novel structure is developed to provide a constant delay at
any divider setting. In addition, input jitter can be isolated to avoid
coupling by digital processing. Hence, the generated clock output
becomes more clean and robust. Based on the proposed methodology, a test
chip has been designed and verified on 0.6-μm CMOS process with
frequency range of (360 ~ 800) MHz at 3.3 V and peak-to-peak jitter of
less than 60 ps at 800 MHz/3.3 V
IEEE Transactions on Circuits and Systems II Analog and Digital Signal Processing 05/2001;
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ABSTRACT: A 2.4 GHz low noise amplifier has been designed in a standard CMOS
0.35 um process. The transistor model is Bsim3 for 0.35 um process. The
amplifier provides a forward gain of 33 dB with a noise figure only 0.92
dB while drawing 17 mw from a 1.5 V supply. Design simulation results
are presented in this paper
Circuits and Systems, 2000. Proceedings of the 43rd IEEE Midwest Symposium on; 02/2000
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ABSTRACT: A dynamic ADC sampling methodology based on error-tracking loop is
proposed in this paper to improve synchronized performance in DSSS
baseband transceivers. To maintain the synchronized performance the ADC
sampling rate is controlled by error-tracking loop to let clock offset
become lower. For 1.8 MHz clock offset based on 44 MHz ADC sampling rate
the BER of DSSS baseband transceivers can achieve 10<sup>-5</sup> in
AWGN channel
Circuits and Systems, 2000. Proceedings of the 43rd IEEE Midwest Symposium on; 02/2000
