[Show abstract][Hide abstract] ABSTRACT: We have used the strain sensitive tool two-dimensional reciprocal space mapping (2D-RSM) and high resolution rocking curves (HR-RC) to assess the effect of the layer thickness and the influence of low temperature Si buffer on the properties of fully relaxed Ge on Si (0 0 1). The samples were grown by chemical vapor deposition in an ASM commercial reactor. As complementary measurements we have employed secondary ion mass spectrometry (SIMS) for chemical analysis, cross sectional transmission electron microscopy for quality assessment, and finally atomic force microscopy (AFM) for investigating the surface roughness. The investigated samples have a thickness ranging from 0.25 to 5.0 m. In addition and for a 5.0 m thick Ge layer, an initial low temperature Si (LT-Si) template was grown before the Ge epitaxy. The results indicate that high quality fully relaxed Ge layers have been achieved using the adopted growth procedure. Most of the improvement in crystalline quality was observed for Ge layers with thickness up to 1.5 m. Above this thickness the observed crystalline quality improvement was negligible. The LT-Si buffer observed to be disadvantageous for pure relaxed Ge growth.
Journal of Materials Science Materials in Electronics 01/2004; 15(7):411-417. · 1.97 Impact Factor
[Show abstract][Hide abstract] ABSTRACT: The strain-sensitive X-ray two-dimensional reciprocal space mapping diffractrometry (2D-RSM) is employed to investigate the relaxation parameters and defect propagation in various thin relaxed buffer layers (RBLs) having a pure Ge top. In addition, we also studied the effect of in situ post-growth thermal treatments at an early growth stage of RBLs with low and intermediate Ge fraction. Both direct Ge epitaxy and multi-layer step-graded epitaxy have been adopted to grow these RBLs using chemical vapor deposition (CVD) at elevated partial pressure (around 10 Torr), which implies a much higher growth rate than RBLs grown using ultra-high vacuum CVD technique. Fully relaxed Ge top layers were obtained for both the direct Ge epitaxy, as well as for the step-graded technique. The results, when comparing these two techniques, favor the direct Ge epitaxy. However, the results of in situ post-growth annealing of the step-graded RBLs indicate a large reduction in the threading dislocations present in the grading regions without a change of relaxation degree or Ge% incorporation in that region.
[Show abstract][Hide abstract] ABSTRACT: We study the device characterization of Si-on-insulator (SOI) metal-oxide-semiconductor field effect transistor (MOSFET) with buried Si1−xGex quantum well (QW) channel. Accurate quantum mechanical description of the p-channel of the buried Si1−xGex QW shows that the peak carrier concentration in the conduction channel is higher in the positively graded SiGe QW, whereas the carriers are more uniformly distributed in the retrograded QW. By phenomenologically introducing a physical parameter to describe the energy relaxation of transmitting wave due to various scattering processes, systematic simulation about quantum wave transmissions of our SOI MOSFET indicates normal current-bias characteristics at nanometre regime. A threshold gate bias of about 0.6 V is obtained for both the positively graded and retrograded SiGe QWs.
Physica E Low-dimensional Systems and Nanostructures 04/2001; 9(4):694-700. · 1.86 Impact Factor
[Show abstract][Hide abstract] ABSTRACT: Double-crystal x-ray diffraction rocking curves and two-dimensional reciprocal space mapping (2D-RSM) are utilized to characterize the degree of strain relaxation, lattice parameters and assessment of defect propagation in two growth approaches to yield relaxed germanium buffer layers on silicon substrates. Two schemes are investigated: direct epitaxy of a single relaxed buffer layer (SE-RBL) and step-graded multiple relaxed buffer layers (GM-RBLs). The characteristics of these two growth schemes offer prospects of a much thinner grown layer compared with previously reported approaches. Two-dimensional reciprocal space mapping shows that an SE-RBL with a thickness of less than 0.35 µm has a superior quality over the GM-RBLs. A high relaxation factor (R = 0.986±0.002) is obtained from the asymmetric (113) 2D-RSM of the SE-RBL with 100% Ge content. Further, the ratios of full width at half maximum of the layer to substrate FWHM (L/S) of nearly unity for both ω and ω/2θ scan directions imply a very high-quality crystalline relaxed buffer layer is realized. The 2D-RSM of the material deposited using the GM-RBL scheme, the first of its kind regarding the total grown thickness (approximately 6 µm), also show a mosaic final Ge buffer layer with an indication of reduction of dislocation density.
Semiconductor Science and Technology 06/2000; 15(7):L25. · 2.21 Impact Factor
[Show abstract][Hide abstract] ABSTRACT: We have used the direct and strain sensitive double crystal and multi-crystal high resolution x-ray diffraction to perform double crystal rocking curves (DC-HRRC) and triple axis high resolution 2-D reciprocal space mapping (2D-RSIM) respectively, as the main tool to assess the relaxation and defect propagation in Ge and Si<sub>1-x</sub> relaxed buffers layers grown on Si (001) substrates. The present study represents one of the first studies regarding the direct extraction and assessment of relaxation parameters and defect propagation in relaxed buffer layers having top pure Ge fully relaxed layer. This technique allows the direct and accurate determination of the mismatches of the lattice parameters parallel and perpendicular to growth directions with an accuracy of 10<sup>-5</sup>. The investigated heterostructures include Ge/Si single epitaxial relaxed buffer layer (SE-RBL) and step graded multi layer Si<sub>1-x</sub>/Si relaxed buffer layer (SG-RBL) with Ge fractions of x=0.15, 0.44 and final pure Ge top layer. Moreover, the effect of post processing annealing is investigated for different temperature time cycles for some of these structures. The unique thin total grown thickness (maximum of 6 μm) actually enables the use of the high resolution X-ray diffraction
High Performance Electron Devices for Microwave and Optoelectronic Applications, 2000 8th IEEE International Symposium on; 02/2000
[Show abstract][Hide abstract] ABSTRACT: A comprehensive electrical characterisation of the SiGe/Si heterostructures has been per-formed in the wide temperature range (10270 K). Four structures fabricated by the Ge + ion implanta-tion technique at different substrate temperatures (room temperature, 150°C, 450°C and 600°C) have been studied. The diode I-V characteristics, thermally stimulated capacitance and currents were meas-ured and the presence and parameters of shallow trap levels were determined in dependence on the substrate temperature. The sample implanted at 450°C shows the best diode operation reflecting the higher quality of the surface silicon layer as compared to RT-and 150°C-implanted samples. Implanta-tion-induced mechanical stresses have been investigated by Raman spectroscopy. For the first time the cryogenic TSCR technique has been applied to this system which makes it possible to investigate strain in the silicon layer due to SiGe layer formation.
[Show abstract][Hide abstract] ABSTRACT: An analytical model for a double QW-PMOS is developed for the determination of the threshold voltages and an estimate of the hole densities in each conducting QW-channel including the silicon surface channel. Detailed analysis of the uncoupled retrograded double QW-PMOS is carried out with varying structural and physical parameters. The model adequately describes and predicts the best design choice of the double QW structure for optimum device performance. The procedure for the evaluation of the optimum structure is not just limited to QW-PMOSs in bulk silicon technology but can be also successfully applied for realizing QW-NMOS structures on relaxed buffer layers.
Semiconductor Science and Technology 12/1998; 13(9):999. · 2.21 Impact Factor
[Show abstract][Hide abstract] ABSTRACT: Single and double Si1−xGex/Si quantum well (QW) structures, which were grown by atmospheric pressure chemical vapor deposition (APCVD), are characterized by photoluminescence and secondary-ion mass spectrometry. Systematic post-growth annealing treatments are carried out at temperatures between 600 and 1100°C in pure N2 ambient. The interdiffusion between the Si layer and the Si1−xGex well layers occurs at the annealing temperature around 900°C. From SIMS measurements for single QW structures we have estimated the activation energy which is about 3.9 eV in the temperature range between 950°C and 1100°C. The double QW structures show a similar value. The intensity of the exciton recombination related to carriers confined in the double QW structures decreases with increasing annealing temperatures and becomes strongly suppressed at 750°C. When the annealing temperature is increased further, the intensity of the QW emission recovers in the QW structures.
Journal of Crystal Growth 10/1998; 193(3):328-334. · 1.69 Impact Factor
[Show abstract][Hide abstract] ABSTRACT: A comprehensive electrical characterisation of the SiGe/Si heterostructures has been performed in the wide temperature range (10-270 K). For this study the structures fabricated by the ion implantation technique at three different substrate temperatures (room temperature, 150 C and 450 C) have been used. The presence and parameters of shallow and deep levels and the diode performance were studied as a function of the substrate temperature. The sample implanted at 450 C shows the best diode operation reflecting the higher quality of the surface silicon layer as compared to RT- and 150 C-implanted samples. For the first time the cryogenic TSCR technique has been applied to this system which makes it possible to investigate strain in the silicon layer due to SiGe layer formation.
[Show abstract][Hide abstract] ABSTRACT: The limitation of the semiclassical description of the charge distribution in the thin, strained buried overlayer of the silicon-on-insulator (SOI) substrate is seen as a hinderance to the progress in device modelling and engineering when using this advanced electronic material technology. A self-consistent solution of the Schrödinger and Poisson equation is carried out to determine the hole distribution in the SiGe quantum well (QW) with a positively and negatively graded trapezoidal Ge profile grown on a SOI substrate. From a thorough analysis of the gate charge control, we predict that the improved hole confinement and channel mobility in the SiGe QW can be maximized over a wide gate voltage range using a negatively graded trapezoidal Ge profile. In addition a much thinner silicon cap layer thickness, with reduced interface scattering, can be used for the retrograded Ge profile.