B. Ghyselen

Publications (15)4.49 Total impact

• Article: New layer transfers obtained by the SmartCut process

  H. Moriceau, F. Fournel, B. Aspar, B. Bataillou, A. Beaumont, C. Morales, A. M. Cartier, S. Pocas, C. Lagahe, E. Jalaguier, [......], F. Letertre, O. Rayssac, I. Cayrefourcq, C. Richtarch, N. Daval, C. Aulentte, T. Akatsu, B. Osternaud, B. Ghyselen, C. Mazuré
  [show abstract] [hide abstract]
  ABSTRACT: The SmartCut process was first developed to obtain silicon-on-insulator (SOI) materials. Now an industrial process, the main Unibond SOI-structure trends are reported in this paper. Many material combinations can be achieved by this process, because it appears to enable the generic development of new structures. Several of the new structures combining different materials and different bonding layers are described. These include SiGe and strained-Si films onto an oxidized Si wafer, silicon-on-insulating multilayer (SOIM) structures, and InP or 4H-SiC film transfers onto low-cost substrates via metallic or even refractory conductive-film bonding layers. More recently, an original bonding process based on mark patterning, wafer bonding, and layer transfer has been proposed to obtain structures in which the relative crystalline-axis orientations of both the film and the substrate can be controlled accurately. In this case, a SmartCut process that includes a mark-patterning step appears well suited for precise control of axis orientations. A procedure is described to obtain an ultra-thin Si film bonded onto a Si wafer. An example of a pure screw-dislocation network achieved by the mark patterning, bonding, and layer-transfer process is reported in this paper. The results have important implications for nanostructure development.
  Journal of Electronic Materials 04/2012; 32(8):829-835. · 1.47 Impact Factor
• Article: The generic nature of the Smart-Cut® process for thin film transfer

  B. Aspar, H. Moriceau, E. Jalaguier, C. Lagahe, A. Soubie, B. Biasse, A. M. Papon, A. Claverie, J. Grisolia, G. Benassayag, F. Letertre, O. Rayssac, T. Barge, C. Maleville, B. Ghyselen
  [show abstract] [hide abstract]
  ABSTRACT: The Smart-Cut® process, based on ion implantation (hydrogen, helium) and wafer bonding, appears more and more as a generic process. The first part of the paper is dedicated to the specific case of thermally-induced splitting. Cavity growth by the Ostwald ripening mechanism and crack propagation are responsible for thermally-induced splitting. In this case, the splitting kinetics are controlled by hydrogen diffusion. In the second part, the latest results concerning new structures are presented.
  Journal of Electronic Materials 04/2012; 30(7):834-840. · 1.47 Impact Factor
• Chapter: Advanced High-Mobility Semiconductor-on-Insulator Materials

  B. Ghyselen, I. Cayrefourcq, M. Kennard, F. Letertre, T. Akatsu, G. Celler, C. Mazure
  [show abstract] [hide abstract]
  ABSTRACT: Silicon-on-Insulator (SOI) is today the substrate of choice for several applications. In order to boost further circuit performance, new solutions are being explored. In particular, increasing the charge carrier mobility has been identified as a requirement for the next technology nodes. One possible option is to increase transistor channel mobility through local strain engineering via external Stressors, an approach that can be used on bulk silicon as well as standard SOI substrates. Other solutions are based on substrate engineering. The attractiveness of these solutions is largely due to their compatibility with standard CMOS integration processes and architectures and presents the advantage of being independent of transistor geometry. The two approaches can be combined to maximize transistor mobility and on-current. Among the different substrate level approaches, we will focus on three main families: (1) the effect of crystal orientation, (2) strained Si and/or SiGe layers On Insulator, and (3) monocrystalline Ge-On-Insulator substrates.
  12/2007: pages 43-72;
• Conference Proceeding: Evaluation of 300 mm High Resistivity SOI UNIBOND material for RF applications up to millimeter wave using 65 nm CMOS SOI technology

  F. Gianesello, C. Raynaud, D. Gloria, S. Boret, B. Ghyselen, C. Mazure
  [show abstract] [hide abstract]
  ABSTRACT: In this paper, 300 mm high resistivity (HR) SOI UNIBONDtrade material is evaluated using RF component and millimeter wave (MMW) function realized in advanced 65 nm HR SOI CMOS technology. The goal is to investigate the insulating behavior, in term of resistivity homogeneity all over the wafer, of 300 mm wafer provided by SOITEC and to offer a benchmarking with well known 200 mm material. For this purpose a methodology based on high frequency measurement is proposed.
  Microelectronic Test Structures, 2007. ICMTS '07. IEEE International Conference on; 04/2007
• Conference Proceeding: Ultra-Thin Fully Depleted SOI Devices with Thin BOX, Ground Plane and Strained Liner Booster

  C. Gallon, C. Fenouillet-Beranger, A. Vandooren, F. Boeuf, S. Monfray, F. Payet, S. Orain, V. Fiori, F. Salvetti, N. Loubet, [......], D. Delille, F. Judong, C. Perrot, M. Hopstaken, P. Scheblin, P. Rivallin, L. Brevard, O. Faynot, S. Cristoloveanu, T. Skotnicki
  [show abstract] [hide abstract]
  ABSTRACT: The fully depleted (FD) SOI MOSFET is generally considered as one of the best candidates for next CMOS technology nodes. However, new technological boosters need to be introduced in the classical FD SOI process flow to reach the very aggressive I_on/I_off specifications predicted by the ITRS roadmap. The use of a thin buried oxide (BOX) on FD SOI is still a controversial subject, despite recent publications that have demonstrated its interest for improvement of short channel effect (SCE) control, especially with a ground plane (GP) integration (Tsuchiya et al.). In order to improve the device performances, a strained "contact etch stop layer" (CESL) technique has been successfully demonstrated to induce strain into the channel of bulk devices (Thompson et al., 2002) as well as in ultra-thin FD SOI devices (Singh et al., 2005 and Gallon et al., 2006). However, its compatibility with the specific technological features of FD SOI devices, such as silicon film thickness (T_S1) variations, BOX material and BOX thickness (T_BOX), raised source/drain architecture, has yet to be clarified. In this paper, we demonstrate, by electrical and mechanical simulations, the interest of thin BOX with GP, combined with a strained liner. These simulations have then been validated by measurements, showing excellent I_on/I_off pMOS performances
  International SOI Conference, 2006 IEEE; 11/2006
• Conference Proceeding: Co-integrated dual strained channels on fully depleted sSDOI CMOSFETs with HfO2/TiN gate stack down to 15nm gate length

  F. Andrieu, T. Ernst, O. Faynot, Y. Bogumilowicz, J.-M. Hartmann, J. Eymery, D. Lafond, Y.-M. Levaillant, C. Dupre, R. Powers, F. Fournel, C. Fenouillet-Beranger, A. Vandooren, B. Ghyselen, C. Mazure, N. Kernevez, G. Ghibaudo, S. Deleonibus
  [show abstract] [hide abstract]
  ABSTRACT: We report an original dual channel fully depleted CMOSFET architecture on insulator (DCOI) co-integrating strained-Si (nMOS) and strained-Si_0.6Ge_0.4 (pMOS) with HfO₂/TiN gate stacks down to 15nm gate length. We demonstrate for the first time an I_ON improvement for short channel SOI of 10% at 35nm gate length (25% at 75nm, 100% on long channels) for both n- and p-MOSFETs and a more than 3 decades gate leakage reduction compared to a SiO₂ dielectric. Meanwhile, thanks to the dual channel engineering, a threshold voltage adjustment is performed with a mid gap single metal gate suitable for high performance (HP) CMOS.
  SOI Conference, 2005. Proceedings. 2005 IEEE International; 11/2005
• Conference Proceeding: In-depth study of strained SGOI nMOSFETs down to 30nm gate length

  F. Andrieu, T. Ernst, O. Faynot, O. Rozeau, Y. Bogumilowicz, J.-M. Hartmann, L. Brevard, A. Toffoli, D. Lafond, H. Dansas, B. Ghyselen, F. Fournel, G. Ghibaudo, S. Deleonibus
  [show abstract] [hide abstract]
  ABSTRACT: Partially depleted floating body transistors on SGOI down to 30nm gate length were fabricated and characterized. They demonstrate excellent static and RF performances. In particular, SGOI 40nm transistors exhibit at V_D=1V a 840μA/μm I_ON at 0.8V gate voltage overdrive (V_GT) vs. 20μA/μm I_OFF at V_GT = -0.2V and a maximum oscillation frequency (f_max) estimated to be 150 GHz at V_G=0.4V. The SGOI originality concerning the floating body effects and the short channel transport were studied in-depth to evaluate this architecture potentiality.
  Solid-State Device Research Conference, 2005. ESSDERC 2005. Proceedings of 35th European; 10/2005
• Chapter: Smart Cut Technology: The Path for Advanced SOI Substrates

  H. Moriceau, C. Lagahe-Blanchard, F. Fournel, S. Pocas, E. Jalaguier, P. Perreau, C. Deguet, T. Ernst, A. Beaumont, N. Kernevez, J.M. Hartman, B. Ghyselen, C. Aulnette, F. Letertre, O. Rayssac, B. Faure, C. Richtarch, I. Cayrefourq
  [show abstract] [hide abstract]
  ABSTRACT: In microelectronics, photonics, opto-electronics, high frequency or high power device applications, the needs for specific substrate solutions are more and more required. Smart Cut™ technology appears as the technological answer that enables the industrial to provide engineered substrate solutions tailored to the applications. For instance a large spectrum of SOI type structures are today in volume manufacturing. At present the industrial is focused on composite substrates. This paper focuses on the realization of advanced SOI, strained SOI, SOQ substrates and many other examples of engineered substrates. Highlights are given on the most recent developments.
  12/2004: pages 39-52;
• Conference Proceeding: Transfer of patterned Si and SiO2 layers for the fabrication of patterned and mixed SOI

  H. Moriceau, C. Yalicheff, C. Gorla, A.M. Charvet, C. Morales, M. Zussy, J. Dechamp, N. Kernevez, F. Letertre, B. Ghyselen, C. Mazure, C. Lagahe-Blanchard, B. Aspar
  [show abstract] [hide abstract]
  ABSTRACT: To illustrate the challenges and potential of advanced wafer bonding, this paper deals with the boding of silicon wafers, which are patterned and partially oxidized. Two kinds of bonded structures are reported. The buried oxide is patterned in thick and thin regions. The bonded interface can be formed by either Si or SiO₂ onto either SiO₂ or mixed Si-SiO₂ bonding (MSOI structures). In the second case, the pattern of the handle wafer is composed by Si and SiO₂ structures onto which a Si layer is transferred. The bonded interface is formed by Si/Si and Si/SiO₂ mixed bonding (PSOI) leading to isolated SOI structures.
  SOI Conference, 2004. Proceedings. 2004 IEEE International; 11/2004
• Conference Proceeding: Multiple SOI layers by multiple Smart-Cut(R) transfers

  C. Maleville, T. Barge, B. Ghyselen, A.J. Auberton, H. Moriceau, A.M. Cartier
  [show abstract] [hide abstract]
  ABSTRACT: Silicon on insulator (SOI) technologies are now entering mainstream applications, with recent announcements regarding for instance microprocessor applications. One condition for this to happen has been proof that SOI material manufacturing processes exist that are compatible with such industrial developments (availability, cost, quality, etc.). Among those processes, the Smart-Cut^(R) process is based on layer transfer from one substrate to another (Bruel, 1996). Stacking monocrystalline silicon on another silicon substrate with a silica layer in between is then possible and indeed is being used on a industrial scale to manufacture SOI wafers. Beyond simple SOI wafers that can also be high value added substrates for other applications such as photonics, sensors and other micromachining purposes, we demonstrate in this paper how the Smart-Cut^(R) process can be seen as a basic step and how this process can be used to realize multiple SOI wafers, allowing different crystalline and/or amorphous layers to be stacked
  SOI Conference, 2000 IEEE International; 02/2000
• Conference Proceeding: Smart-Cut(R) process: an original way to obtain thin films by ion implantation

  B. Aspar, C. Lagahe, H. Moriceau, A. Soubie, E. Jalaguier, B. Biasse, A. Papon, A. Chabli, A. Claverie, J. Grisolia, G. Benassayag, T. Barge, F. Letertre, B. Ghyselen
  [show abstract] [hide abstract]
  ABSTRACT: The Smart-Cut(R) process, based on proton implantation and wafer bonding, appears more and more as a generic process. The first part of the paper is dedicated to the specific case of thermally induced splitting. Cavity growth by Ostwald ripening mechanism and crack propagation are responsible for thermally-induced splitting. In this case, the splitting kinetics are controlled by hydrogen diffusion. In the second part, the latest results concerning new structures are presented
  Ion Implantation Technology, 2000. Conference on; 02/2000
• Article: Fully depleted silicon on insulator MOSFETs on (110) surface for hybrid orientation technologies

  T. Signamarcheix, F. Andrieu, B. Biasse, M. Cassé, A.-M. Papon, E. Nolot, B. Ghyselen, O. Faynot, L. Clavelier
  [show abstract] [hide abstract]
  ABSTRACT: An alternative technology is studied here to elaborate hybrid orientation silicon on insulator (SOI) films above a continuous buried oxide (BOX). To this purpose, a “deep-amorphization” followed by solid phase epitaxial regrowth (SPER) of SOI films is investigated. The effect of the deep-amorphization and SPER on p-type fully-depleted metal oxide semiconductor field effect transistors (FD-MOSFETs) electrical characteristics is presented and discussed for both (1 0 0) and (1 1 0) oriented SOI films. High performance pMOS were realized on (1 1 0) substrates. Our results show a +30% gain on the drive current for the (1 1 0) surface orientation, and we further demonstrate that no degradation of the performance is introduced by the amorphization and SPER processes.Highlights► We examine the performances of fully-depleted transistor made on specific (1 1 0) oriented SOI. ► Impact of a deep amorphization and SPER is studied on SOI substrates. ► An alternative process to locally convert the orientation of an SOI film is studied.
  Solid-State Electronics. 59(1):8-12.
• Article: Strain characterization of strained silicon on insulator wafers

  V Paillard, B Ghyselen, C Aulnette, B Osternaud, N Daval, F Fournel, H Moriceau, T Ernst, J.M Hartmann, C Lagahe-Blanchard, S Pocas, P Leduc, L Vincent, F Cristiano, Y Campidelli, O Kermarrec, P Besson, Y Morand
  [show abstract] [hide abstract]
  ABSTRACT: We show that it is possible to combine both silicon on insulator and strained silicon structures, which are usually considered as independent solutions to improve the performance of silicon-based CMOS transistors. Using Raman spectrometry and electron microscopy, we studied one kind of virtual Si1−xGex substrate produced by reduced pressure-chemical vapor deposition, and the strained silicon thin film grown on top of this substrate. These structures are transferred on a silicon substrate using the SMART CUTTM process to form strained silicon on insulator wafers (SSOI). The main result is that the overlayers in the silicon on insulator structures keep the same stress than they had before transfer. The stress, measured in SSOI wafers with Si layers as thin as 10 nm, is not affected by high temperature annealing up to 1000 °C.
  Microelectronic Engineering 72:367-373. · 1.56 Impact Factor
• Conference Proceeding: 25nm Short and Narrow Strained FDSOI with TiN/HfO2 Gate Stack

  F. Andrieu, C. Dupre, F. Rochette, O. Faynot, L. Tosti, C. Buj, E. Rouchouze, M. Casse, B. Ghyselen, I. Cayrefoureq, [......], C. Fenouillet-Beranger, C. Jahan, D. Lafond, H. Dansas, B. Previtali, J.P. Colonna, H. Grampeix, P. Gaud, C. Mazure, S. Deleonibus
  [show abstract] [hide abstract]
  ABSTRACT: We investigate for the first time the experimental performance of strained silicon directly on insulator (sSOI) for short and narrow FDSOI NMOS transistors integrated with a TiN/HfO₂ gate stack. A +16% drive current improvement is reported for a 25nm gate length (among the best ever reported for short substrate-induced strained devices). Through in-depth electrical characterization and mechanical simulations, transition from bi-axial to uni-axial strain is evidenced in extremely narrow sSOI channels, with a 40% mobility enhancement for 35nm wide devices. This highlights that the strain is not lost at sub-40nm dimensions
  VLSI Technology, 2006. Digest of Technical Papers. 2006 Symposium on;
• Article: Performance and physics of sub-50nm strained Si on Si1−xGex-on-insulator (SGOI) nMOSFETs

  F. Andrieu, T. Ernst, O. Faynot, O. Rozeau, Y. Bogumilowicz, J.-M. Hartmann, L. Brévard, A. Toffoli, D. Lafond, B. Ghyselen, F. Fournel, G. Ghibaudo, S. Deleonibus
  [show abstract] [hide abstract]
  ABSTRACT: Partially depleted floating body transistors on SGOI down to 30 nm gate length were fabricated and characterized. They demonstrate excellent static and RF performance. In particular, 40 nm gate length SGOI transistors exhibit a maximum oscillation frequency (fmax) estimated to be 150 GHz at VG = 0.4 V. The SGOI originality concerning the floating body effects, the RF characteristics and the short channel transport were in-depth studied in order to evaluate this architecture potentiality.
  Solid-State Electronics.