N. Shaikh-Husin

Publications (5)0 Total impact

• Source

  Available from: psu.edu

  Conference Proceeding: Implementation of recurrent neural network algorithm for shortest path calculation in network routing

  N. Shaikh-Husin, M.K. Hani, Teoh Giap Seng
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  ABSTRACT: This paper describes the architecture and implementation of a shortest-path processor, both in reconfigurable hardware and VLSI. This processor is based on the principles of a recurrent spatiotemporal neural network. The processor's operation is similar to E.W. Dijkstra's (1959) algorithm and it can be used for network routing calculations. The objective of the processor is to find the least-cost path in a weighted graph between a given node and one or more destinations. The digital implementation, which exhibits a regular interconnect structure and uses simple processing elements, is well-suited for VLSI implementation and reconfigurable hardware
  Parallel Architectures, Algorithms and Networks, 2002. I-SPAN '02. Proceedings. International Symposium on; 02/2002
• Source

  Available from: utm.my

  Conference Proceeding: FPGA implementation of RSA public-key cryptographic coprocessor

  M.K. Hani, Tan Siang Lin, N. Shaikh-Husin
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  ABSTRACT: The hardware implementation of the RSA algorithm for public-key cryptography is presented. The algorithm is dependent on the computation of modular exponentials. Critical to this computation is a fast implementation of modular multiplications. A high-performance systolic array architecture for modular multiplication based on the algorithm of Montgomery (1985) is proposed. The design is targeted for implementation in reconfigurable logic, which can yield custom-hardware performance yet maintains all the flexibility of software-based systems. Reconfigurable computing allows the designer to respond, in the prototyping stage, to flaws discovered in implementation or to changes in standards or data formats. We report the issues involved in the preliminary design of the prototype to be fabricated in Altera FLEX10KE series FPGA mounted on a PCI card
  TENCON 2000. Proceedings; 02/2000
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  Available from: utm.my

  Conference Proceeding: Pulse coded neural network implementation in VLSI

  N. Shaikh-Husin, Chang Wooi Po
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  ABSTRACT: A neural network that encodes signals in terms of pulses has been designed and fabricated. The neural network components are described in detail. As a test case, a two-layer network is implemented. A preliminary test result shows some promise and some limitations of the design
  TENCON 2000. Proceedings; 02/2000
• Conference Proceeding: Spatiotemporal neural networks for link-state routing protocols

  N. Shaikh-Husin, J.L. Meador
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  ABSTRACT: This paper discusses the application of a mixed-signal VLSI realization of a recurrent spatiotemporal neural network to a computer network routing. The neural network exhibits a regular interconnect structure and uses simple processing units in a combination which is well suited for VLSI implementation with a standard fabrication process. Its ability to rapidly arrive at solutions to the single-source multiple-destination routing problem makes it particularly attractive for link-state network routing protocols
  Circuits and Systems, 1996. ISCAS '96., Connecting the World., 1996 IEEE International Symposium on; 06/1996
• Conference Proceeding: Mixed signal neural circuits for shortest path computation

  N. Shaikh-Husin, J.L. Meador
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  ABSTRACT: The objective of the graphical shortest path problem is to discover the least cost path in a weighted graph between a given source vertex and one or more destinations. This problem class has numerous practical applications including data network routing and speech recognition. This paper discusses the hardware realization of a recurrent spatiotemporal neural network for single source multiple-destination graphical shortest path problems. The network exhibits a regular interconnect structure and uses simple processing units in a combination which is well suited for VLSI implementation with a standard fabrication process.
  Signals, Systems and Computers, 1995. 1995 Conference Record of the Twenty-Ninth Asilomar Conference on;