Y. Taur

University of California, San Diego, San Diego, CA, United States

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Publications (98)79.71 Total impact

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    ABSTRACT: A 23.8-GHz tuned amplifier is demonstrated in a partially scaled 0.1-μm silicon-on-insulator CMOS technology. The fully integrated three-stage amplifier employs a common-gate, source-follower, and cascode with on-chip spiral inductors and MOS capacitors. The gain is 7.3 dB, while input and output reflection coefficients are -45 and -9.4 dB, respectively. Positive gain is exhibited beyond 26 GHz. The amplifier draws 53 mA from a 1.5-V supply. The measured on-wafer noise figure is 10 dB, while the input-referred third-order intercept point is -7.8 dBm. The results demonstrate that 0.1-μm CMOS technology may be used for 20-GHz RF applications and suggest even higher operating frequencies and better performance for further scaled technologies
    IEEE Transactions on Microwave Theory and Techniques 10/2002; · 2.23 Impact Factor
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    ABSTRACT: This paper presents a dual supply voltage strategy for reduction of the total (static and dynamic) power of high performance CMOS processors. By expressing CMOS delay, static power, and dynamic power in terms of the power supply voltage V<sub>DD</sub> and threshold voltage V<sub>T</sub>, an optimization procedure that takes the circuit activity factor into account is performed to find the V<sub>DD</sub> and V<sub>T</sub> for minimum total power at given performance levels. It is shown that 50% power reduction or 20% performance enhancement can be attained by adopting both a low (0.5 V) supply voltage for high-activity circuits and a high (1.2 V) supply voltage for low-activity circuits in a 100 nm-node CMOS technology.
    VLSI Technology, 2002. Digest of Technical Papers. 2002 Symposium on; 02/2002
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    Y. Taur
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    ABSTRACT: Beginning with a brief review of CMOS scaling trends from 1 µm to 0.1 µm, this paper examines the fundamental factors that will ultimately limit CMOS scaling and considers the design issues near the limit of scaling. The fundamental limiting factors are electron thermal energy, tunneling leakage through gate oxide, and 2D electrostatic scale length. Both the standby power and the active power of a processor chip will increase precipitously below the 0.1-µm or 100-nm technology generation. To extend CMOS scaling to the shortest channel length possible while still gaining significant performance benefit, an optimized, vertically and laterally nonuniform doping design (superhalo) is presented. It is projected that room-temperature CMOS will be scaled to 20-nm channel length with the superhalo profile. Low-temperature CMOS allows additional design space to further extend CMOS scaling to near 10 nm.
    Ibm Journal of Research and Development 01/2002; 46(2-3):213-222. · 0.69 Impact Factor
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    ABSTRACT: First Page of the Article
    Solid-State Device Research Conference, 2001. Proceeding of the 31st European; 10/2001
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    ABSTRACT: Dual-phase dynamic pseudo-NMOS ([DP]<sup>2</sup>) frequency dividers have been implemented in a partially scaled 0.1 μm CMOS technology. For 4:1 dividers on silicon-on-insulator (SOI) and bulk substrates, the maximum speed, power consumption, and extracted [DP]<sup>2</sup> latch delays are 18.75 and 15.4 GHz, 13.5 and 9.8 mW and 13.3 and 16.2 ps, respectively, at 1.5 V
    Electronics Letters 06/2001; · 1.04 Impact Factor
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    ABSTRACT: This paper presents the current state of understanding of the factors that limit the continued scaling of Si complementary metal-oxide-semiconductor (CMOS) technology and provides an analysis of the ways in which application-related considerations enter into the determination of these limits. The physical origins of these limits are primarily in the tunneling currents, which leak through the various barriers in a MOS field-effect transistor (MOSFET) when it becomes very small, and in the thermally generated subthreshold currents. The dependence of these leakages on MOSFET geometry and structure is discussed along with design criteria for minimizing short-channel effects and other issues related to scaling. Scaling limits due to these leakage currents arise from application constraints related to power consumption and circuit functionality. We describe how these constraints work out for some of the most important application classes: dynamic random access memory (DRAM), static random access memory (SRAM), low-power portable devices, and moderate and high-performance CMOS logic. As a summary, we provide a table of our estimates of the scaling limits for various applications and device types. The end result is that there is no single end point for scaling, but that instead there are many end points, each optimally adapted to its particular applications
    Proceedings of the IEEE 04/2001; · 6.91 Impact Factor
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    ABSTRACT: Demonstrated double-gate devices with excellent drive current and short-channel-effect control. The double-gate devices exhibit ideal linear, sub-threshold slope of 60 mV/dec and better than ideal saturated sub-threshold slope of 55 mV/dec. The effective mobility in all device structures follows the universal mobility curve. The symmetric double-gate offers 20% mobility enhancement over a GP device at 1.0 V gate over-drive. Because the double-gate can be operated at a much lower effective-field, substantial mobility enhancement (>2X) over scaled bulk CMOS can be achieved. For the first time, DC operation of double-gate CMOS inverters are demonstrated down to Vdd=0.3 V
    Electron Devices Meeting, 2001. IEDM Technical Digest. International; 02/2001
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    ABSTRACT: A bulk silicon divide-by-two dynamic frequency divider with maximum clock speed of 26.5 GHz has been achieved. The dynamic divider operates from 6.5 GHz to 26.5 GHz. The design is based on n-channel MOSFET's with an effective gate length of 0.1 μm
    IEEE Microwave and Guided Wave Letters 11/2000;
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    ABSTRACT: In this paper, the performance of 25 nm double-gate, back-gate and super-halo CMOS devices has been analyzed, including the self-consistent 2D quantization effect. The drive current is enhanced by the gate-to-body coupling effect for double-gate with ultra-thin body. The channel quantization effect can substantially degrade the drive current for asymmetric double-gate, back-gate, and bulk CMOS ICs. It is demonstrated that the exceptional SCE immunity in SDG offers substantial performance leverage over conventional MOSFET structures
    Simulation of Semiconductor Processes and Devices, 2000. SISPAD 2000. 2000 International Conference on; 02/2000
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    ABSTRACT: This paper presents a new 3D Monte Carlo approach for modeling random dopant fluctuation effects in MOSFETs. The method takes every silicon atom in the device into account and is generally applicable to arbitrary nonuniform doping profiles. In addition to body dopant fluctuations, the effect of source-drain dopant fluctuations on short-channel threshold voltage is studied for the first time. The result clearly indicates the benefit of retrograde body doping and shallow/abrupt source-drain junctions. It also quantifies the magnitude of threshold voltage variations due to discrete dopant fluctuations in an optimally designed 25 nm MOSFET
    VLSI Technology, 1999. Digest of Technical Papers. 1999 Symposium on; 02/1999
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    ABSTRACT: Si CMOS technology has steadily grown in importance for the past 30 years until it is now the dominant logic technology in the electronics industry. This talk will briefly describe the current state of Si CMOS and will then concentrate on where it appears to be headed in the next decade or so
    Device Research Conference Digest, 1999 57th Annual; 02/1999
  • Y. Taur
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    ABSTRACT: This paper discusses the issues, challenges, and possible directions for further scaling and performance gains beyond 0.1 μm CMOS. Gate oxides, already down to a few atomic layers thick, will soon be limited by tunneling currents to a thickness of 15-20 Å. A general guideline, based on 2-D effects in MOSFETs, is given for the length scaling of high-k gate dielectrics. A feasible design for 25 mm bulk CMOS is to use a highly abrupt, vertically and laterally nonuniform doping profile to control the short-channel effect. The effect of polysilicon-gate depletion on the performance of 25 nm CMOS is examined and quantified. Beyond conventional CMOS, the question whether any of the exploratory device structures, including ultra-thin SOI and double-gate MOSFET, can extend CMOS scaling to 10 nm channel length is addressed
    VLSI Technology, Systems, and Applications, 1999. International Symposium on; 02/1999
  • Y. Taur, C.H. Wann, D.J. Frank
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    ABSTRACT: This paper explores the limit of bulk (or partially-depleted SOI) CMOS scaling. A feasible design for 25 nm (channel length) CMOS, without continued scaling of oxide thickness and power supply voltage, is presented. A highly 2D nonuniform profile (super-halo) is shown to yield low off-currents while delivering a significant performance advantage for a 1.0 V power supply. Several key issues, including source-drain doping requirements, band-to-band tunneling, and poly depletion effects, are examined and quantified. It is projected, based on Monte-Carlo simulations, that the delay performance of 25 nm CMOS is 3× higher than 100 nm CMOS, and that the nFET f<sub>T</sub> exceeds 250 GHz
    Electron Devices Meeting, 1998. IEDM '98 Technical Digest., International; 01/1999
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    ABSTRACT: The electrical characteristics (C-V and I-V) of n+ - and p+ -polysilicon-gated ultrathinoxide capacitors and FETs were studied extensively to determine oxide thickness and to evaluate tunneling current. A quantum-mechanical model was developed to help understand finite inversion layer width, threshold voltage shift, and polysilicon gate depletion effects. It allows a consistent determination of the physical oxide thickness based on an excellent agreement between the measured and modeled C-V curves. With a chip standby power of ≤0.1 W per chip, direct tunneling current can be tolerated down to an oxide thickness of 15-20 Å. However, transconductance reduction due to polysilicon depletion and finite inversion layer width effects becomes more severe for thinner oxides. The quantum-mechanical model predicts higher threshold voltage than the classical model, and the difference increases with the electric field strength at the silicon/oxide interface.
    Ibm Journal of Research and Development 01/1999; 43(3):327-337. · 0.69 Impact Factor
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    ABSTRACT: Four- and 13-GHz tuned amplifiers have been implemented in a partially scaled 0.1-1 μm CMOS technology on bulk, silicon-on-insulator (SOI), and silicon-on-sapphire (SOS) substrates. The 4-GHz bulk, SOI, and SOS amplifiers exhibit forward gains of 14, 11, and 12.5 dB and F<sub>min</sub>'s of 4.5 (bulk) and 3.5 db (SOS). The 13-GHz SOS and SOI amplifiers exhibit gains of 15 and 5.3 dB and F<sub>unn</sub>'s of 4.9 and 7.8 dB. The 4-GHz bulk amplifier has the highest resonant frequency among reported bulk CMOS amplifiers, while the 13-GHz SOS and SOI amplifiers are the first in a CMOS technology to have tuned frequencies greater than 10 GHz. These and other measurement results suggest that it may be possible to implement 20-GHz tuned amplifiers in a fully scaled 0.1-1 μm CMOS process
    IEEE Journal of Solid-State Circuits 01/1999; · 3.06 Impact Factor
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    ABSTRACT: We derive a new scale length for two-dimensional (2-D) effects in MOSFETs and discuss its significance. This derivation properly takes into account the difference in permittivity between the Si channel and the gate insulator, and thus permits an accurate understanding of the effects of using insufficiently scaled oxide or thicker higher permittivity gate insulators. The theory shows that the utility of higher dielectric constant insulators decreases for /spl epsiv///spl epsiv//sub 0/>-20, and that in no event should the insulator be thicker than the Si depletion depth. The approach is also applied to double-gated FET structures, resulting in a new more general scale length formula for them, too.
    IEEE Electron Device Letters 11/1998; · 2.79 Impact Factor
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    ABSTRACT: 4-GHz 1.5-V tuned amplifiers are implemented using a partially-scaled double-level-metal 0.1-μm CMOS process on bulk and SOI substrates. The bulk and SOI amplifiers have forward transducer gains (S<sub>21</sub>) of 14 and 11 dB at V<sub>DD</sub>=1.5 V. The bulk amplifier has F<sub>min</sub>'s of 3.6 and 4.5 dB at 3 and 4 GHz, respectively, with a power consumption of about 28 mW. When the supply voltage is reduced to 1.0 V, F<sub>min</sub> is increased to 4.4 and 5.0 dB at 3.0 and 4.0 GHz, while the peak gain and power consumption are lowered to 9 dB and 12.7 mW, respectively, which are not significantly worse than those of 5.8-GHz silicon bipolar LNA's
    Silicon Monolithic Integrated Circuits in RF Systems, 1998. Digest of Papers. 1998 Topical Meeting on; 10/1998
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    ABSTRACT: Sub-tenth-micron CMOS has cut-off frequency reaching 150 GHz and gate delay around 15 ps at 1.5 V. The device speed suggests that CMOS has the potential for RF and microwave applications. Since these short-channel MOSFETs are designed mainly for digital applications, the fine-tuning in device design needed for analog applications is presented. For example, initial observation show relatively low f<sub>max</sub>. Whether this is inherent to sub-tenth-micron MOSFET merits investigation. Noise characteristics, device linearity, and power output capability also demand careful examination. This paper presents some device and circuit results using sub-tenth-micron CMOS, and discusses the directions for RFCMOS device design
    Solid-State Circuits Conference, 1998. Digest of Technical Papers. 1998 IEEE International; 03/1998
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    ABSTRACT: CMOS is a viable contender for front-end receiver circuits in the frequency range between 0.9 and 2 GHz. As gate lengths decrease to 0.1 μm and below, this frequency range will increase, potentially opening up applications such as wireless LANs in the 5-20 GHz range. These 4 GHz and 13 GHz CMOS tuned amplifiers are implemented with partially-depleted silicon on insulator (SOI) and silicon on sapphire (SOS) nMOS transistors with floating bodies. Measured forward gains (S21) for the 4 GHz SOS and SOI amplifiers are 12 and 11 dB, respectively, and 15 and 5.3 dB for the 13 GHz SOS and SOI amplifiers. The 13 GHz amplifiers are the first in a CMOS technology to have tuned frequencies greater than 10 GHz. The CMOS process uses 0.35 μm design rules for all dimensions except for the 0.1 μm gate length and 2.9 nm gate oxide thickness. The nMOS transistors have -100 GHz measured peak f<sub>T</sub>. Threshold voltages are 0.2 and 0.4 V for the SOS and SOI transistors, respectively
    Solid-State Circuits Conference, 1998. Digest of Technical Papers. 1998 IEEE International; 03/1998

Publication Stats

3k Citations
79.71 Total Impact Points

Institutions

  • 2002
    • University of California, San Diego
      • Department of Electrical and Computer Engineering
      San Diego, CA, United States
  • 1999–2002
    • University of Florida
      • Department of Electrical and Computer Engineering
      Gainesville, FL, United States
  • 1994
    • National Tsing Hua University
      • Department of Electrical Engineering
      Hsinchu, Taiwan, Taiwan