S. Barraud

Cea Leti, Grenoble, Rhône-Alpes, France

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Publications (136)175.8 Total impact

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    ABSTRACT: In this paper, we investigate Bias Temperature Instabilities (BTI) in Ωfet nanowires exhibiting a very low interface states density ∼1010 cm2. Positive BTI is independent of the transistor width W and meets the 10 year lifetime requirements. On the other hand, Negative BTI is enhanced in narrow devices. To explain this effect, several scenarios are discussed by means of dedicated measurements i.e. charge pumping, BTI variability and 3D simulations. We first show that the oxide field in this 3D architecture cannot be responsible for this NBTI enhancement. Moreover we demonstrate by correlating NBTI variability and charge pumping measurements, that, the width dependence of NBTI may be explained by a stronger degradation of the interfacial oxide on the sidewall of the nanowire compared to the top interface.
    Microelectronic Engineering 11/2015; 147:10-14. DOI:10.1016/j.mee.2015.04.028 · 1.34 Impact Factor
  • Physical Review X 07/2015; · 8.39 Impact Factor
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    ABSTRACT: Radio-fRequency Reflectom-etry (RfR) is a technique that was developed to characterize the properties of transmission lines by observing reflected waveforms. today, it is widely used in a variety of applications, ranging from the detection of faulty wires in cables [1] and objects buried in the ground [2] to soil moisture detectors [3] and the measurement of dielectric properties of blood [4]. Recently, one important application of this technique, which requires a very small amount of applied power, was developed for the characterization of electronic nanostructures [5]. in this implementation , a microwave radio-frequency (Rf) signal is sent to a resonator coupled to the specimen to be studied. if in a specimen the change of some external parameter (e.g., gate voltage) leads to a change of an active [figure 1(a)] or a reactive (typically, capacitive) load [ figure 1(b)] to the resonator, the self-resonance is affected, resulting in a change of magnitude [figure 2(a)] and phase [figure 2(b)] of the reflected signal. if an impedance matching condition is achieved, the modification of the specimen parameter (e.g., the increase of its resistance) will lead to a very significant change in the reflection coefficient C [figure 2(a)]. Here, we discuss two important applications of the RfR technique on nanoscale devices. first, RfR provides a method for fast (<100 ns) and broadband (in excess of 100 mHz) sensing of single-electron transistors (Sets) [5] and quantum point contacts (qPcs) [6], which are essential readout elements for promising new technologies such as spin quantum bits [7]– [9]. By contrast, the traditional methods of probing these types of devices by measuring changes in their conductance or resistance suffer from very limited band-width (<1 mHz) due to the high impedance of the devices and parasitic input capacitance of the sensing amplifier. in an RfR Set setup [5], the input Rf sine wave (with a frequency in the range of 10 8 –10 9 Hz) is reflected from a tank circuit , typically consisting of a lumped inductor and a parasitic capacitor to ground, acting as an impedance transformer , and the device under test (an Set or qPc) acting as the load. the main purpose of the inductor-capacitor (l-c) impedance transformer is to transform the high impedance of the device under test closer to a standard transmission line resistance , e.g., 50. X Because the impedance transformer typically used in an RfR setup is a resonant circuit, it also provides frequency selectivity, attenuates unwanted signals away from the resonant frequency, and suppresses " pink " /f 1 noise [10]. the second class of applications is the use of RfR-based spectroscopy to enable researchers to " look inside " devices to understand the intricate physical mechanisms of transport on the nanoscale. RfR in this case is used as a unique characterization tool for studying the properties of these devices and the materials of which they are composed. for this class of RfR application , speed and wide bandwidth are typically of lesser concern than obtaining the highest possible sensitivity. even small changes in the device capacitance, for example , as might arise from a single defect level, may be sufficient to produce a detectable signal. the role of the resonator is to increase the sensitivity of the reflected signal (i.e., the magnitude and phase) to changes in the device impedance, thereby easing the detection of small changes (e.g., caused by single-electron charging of an Set island or trapping/detrapping effects near it). the tools developed in the process of pursuing these two applications are complementary so that development in one leads to the progress in the other. for example, improvements in the charge sensitivity of the Rf Set qubit readout enhance the detection capabilities of the charged defect detecting technique.
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    ABSTRACT: We report the observation of an atomic like behavior from T=4.2K up to room temperature, in n and p type Omega-gate silicon nanowire (NW) transistors. For that purpose, we modified the design of a NW transistor and introduced long spacers between the source/drain and the channel, in order to separate the channel from the electrodes. The channel was made extremely small (3.4 nm in diameter with 10 nm gate length) with a thick gate oxide (7nm) in order to enhance the Coulomb repulsion between carriers, which can be as large as 200 meV when surface roughness promotes charge confinement. Parasitic stochastic Coulomb blockade effect can be eliminated in our devices by control voltages. Moreover, the quantum dot can be tuned so that the resonant current at T=4.2 K exceeds that at room temperature.
    Nano Letters 04/2015; 15:2958. DOI:10.1021/nl504806s · 13.59 Impact Factor
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    ABSTRACT: We report the dispersive readout of the spin state of a double quantum dot formed at the corner states of a silicon nanowire field-effect transistor. Two face-to-face top-gate electrodes allow us to independently tune the charge occupation of the quantum dot system down to the few-electron limit. We measure the charge stability of the double quantum dot in DC transport as well as dispersively via in-situ gate-based radio frequency reflectometry, where one top-gate electrode is connected to a resonator. The latter removes the need for external charge sensors in quantum computing architectures and provides a compact way to readout the dispersive shift caused by changes in the quantum capacitance during interdot charge transitions. Here, we observe Pauli spin-blockade in the high-frequency response of the circuit at finite magnetic fields between singlet and triplet states. The blockade is lifted at higher magnetic fields when intra-dot triplet states become the ground state configuration. A lineshape analysis of the dispersive phase shift reveals furthermore an intradot valley-orbit splitting $\Delta_{vo}$ of 145 $\mu$eV. Our results open up the possibility to operate compact CMOS technology as a singlet-triplet qubit and make split-gate silicon nanowire architectures an ideal candidate for the study of spin dynamics.
    Nano Letters 04/2015; 15(7). DOI:10.1021/acs.nanolett.5b01306 · 13.59 Impact Factor
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    ABSTRACT: Silicon-On-Insulator nanowire transistors of very small dimensions exhibit quantum effects like Coulomb blockade or single-dopant transport at low temperature. The same process also yields excellent field-effect transistors (FETs) for larger dimensions, allowing to design integrated circuits. Using the same process, we have co-integrated a FET-based ring oscillator circuit operating at cryogenic temperature which generates a radio-frequency (RF) signal on the gate of a nanoscale device showing Coulomb oscillations. We observe rectification of the RF signal, in good agreement with modeling.
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    ABSTRACT: Electron spin qubits in silicon, whether in quantum dots or in donor atoms, have long been considered attractive qubits for the implementation of a quantum computer due to the semiconductor vacuum character of silicon and its compatibility with the microelectronics industry. While donor electron spins in silicon provide extremely long coherence times and access to the nuclear spin via the hyperfine interaction, quantum dots have the complementary advantages of fast electrical operations, tunability and scalability. Here we present an approach to a novel hybrid double quantum dot by coupling a donor to a lithographically patterned artificial atom. Using gate-based rf reflectometry, we probe the charge stability of this double quantum dot system and the variation of quantum capacitance at the interdot charge transition. Using microwave spectroscopy, we find a tunnel coupling of 2.7 GHz and characterise the charge dynamics, which reveals a charge T2 of 200 ps and a relaxation time T1 of 100 ns. Additionally, we demonstrate spin blockade at the inderdot transition, opening up the possibility to operate this coupled system as a singlet-triplet qubit or to transfer a coherent spin state between the quantum dot and the donor electron and nucleus.
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    ABSTRACT: This work studies, for the first time to our best knowledge, the perspectives of trigate nanowire (TGNW) MOSFETs for analog applications. An effect of nanowire width, length and orientation as well as frequency (up to 4 GHz) and temperature (up to 225 °C) on analog figures-of-merit (FoM) is analyzed. Benchmarking with other advanced devices such as ultra-thin body and BOX (UTBB) MOSFETs and SOI-based FinFETs is presented. TGNW MOSFETs are shown to be very promising for analog applications featuring high transconductance combined with high intrinsic gain. Only a slight reduction of device performance over the frequency and temperature ranges is observed.
    Solid-State Electronics 02/2015; DOI:10.1016/j.sse.2015.02.003 · 1.51 Impact Factor
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    ABSTRACT: A study of the gate oxide/channel interface quality in ultra-scaled SOI omega-gate nanowire NMOS FETs with cross-section as small as 10 nm × 10 nm is experimentally presented by low-frequency noise measurements. The noise study has been efficiently applied for the characterization of various technological parameters, including strained channel, additional hydrogen anneal, or channel orientation difference. A method for rigorous contribution assessment of the two oxide/channel interfaces (top surface vs. side-walls) is also demonstrated. Quality of the interface is slightly altered among the 4-types of technological parameters and the structural variety down to nanowire. However, an excellent quality of Hf-based high-k/metal gate stack is observed and sustained in all the devices. In particular, efficient tensile strain stressor is demonstrated with high enhancement of the NMOS FET performance and preserved 1/f noise performance fulfilling the requirement for future CMOS logic node stated in the international technology roadmap for semiconductors.
    Solid-State Electronics 02/2015; 108. DOI:10.1016/j.sse.2014.12.010 · 1.51 Impact Factor
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    ABSTRACT: uantum computation requires a qubit-specific measurement capability to readout the final state of individual qubits. Promising solid-state architectures use external readout electrometers but these can be replaced by a more compact readout element, an in situ gate sensor. Gate-sensing couples the qubit to a resonant circuit via a gate and probes the qubit’s radiofrequency polarizability. Here we investigate the ultimate performance of such a resonant readout scheme and the noise sources that limit its operation. We find a charge sensitivity of 37 μe Hz−1/2, the best value reported for this technique, using the example of a gate sensor strongly coupled to a double quantum dot at the corner states of a silicon nanowire transistor. We discuss the experimental factors limiting gate detection and highlight ways to optimize its sensitivity. In total, resonant gate-based readout has advantages over external electrometers both in terms of reduction of circuit elements as well as absolute charge sensitivity.
    Nature Communications 01/2015; 6:6084. DOI:10.1038/ncomms7084 · 10.74 Impact Factor
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    ABSTRACT: The less surface roughness scattering effects, owing to the unique operation principle, in junctionless nanowire transistors (JLT-NW) were shown by low-temperature characterization and 2D numerical simulation results. This feature could allow a better current drive under a high gate bias. In addition, the dominant scattering mechanisms in JLT-NW, with both a short (LM = 30 nm) and a long channel (LM = 10 μm), were investigated through an in-depth study of the temperature dependence of transconductance (gm) behavior and compared to conventional inversion-mode nanowire transistors.
    Applied Physics Letters 12/2014; 105(26):263505. DOI:10.1063/1.4905366 · 3.52 Impact Factor
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    ABSTRACT: We have fabricated hybrid channel Ω-gate CMOS nanowires (NWs) with strained SiGe-channel (cSiGe) p-FETs and Si-channel n-FETs. An optimized process flow based on the Ge enrichment technique results in a +135% hole mobility enhancement at long gate lengths compared to Si. Effectiveness of cSiGe channel is also evidenced for ultra-scaled p-FET NWs (gate length L G =15 nm) with +90% I ON current improvement. Introduction NW transistors are today widely recognized as a promising solution to pursue the Moore's law beyond FinFET and Fully-Depleted Silicon-On-Insulator (SOI) CMOS technologies. During the last years, aggressively scaled NW transistors have already been demonstrated [1-3]. We previously showed high-performance uniaxial tensily-strained Ω-gate sSOI n-FET NWs down to 10nm gate length with an excellent electrostatic control [4]. We also recently fabricated and characterized high-performance Ω-gate p-FETs on compressively-strained-SiGeOI substrates obtained by the Ge enrichment technique [5]. Uniaxial compressive strain definitely improved hole transport in those SiGe NWs [5-7]. In this paper, for the first time, we report the successful co-integration of hybrid Si and SiGe channels in high AC performances NW CMOS devices that outperform state-of-the-art SOI nanowires. The strain is measured by using precession electron diffraction with a 1nm spatial resolution. We show that hybrid integration reduces the delay of CMOS ring oscillators (Fan-Out=3) by 50% at V DD =0.9 V. We also demonstrate the most aggressively scaled hybrid CMOS NWs reported to date with NW width and gate length down to 7 nm and 11 nm, while maintaining high drive current (687 µA/µm for p-FET and 647 µA/µm for n-FET) with low leakage current and excellent short-channel-control (DIBL<50 mV/V). Finally, [110]-oriented NW is shown to be the best candidate to improve drive current under compressive strain. Si/SiGe Hybrid Channel Patterning
    IEDM 2014, San Francisco, USA; 12/2014
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    ABSTRACT: The mobility degradation by the relaxed electric-field in junctionless transistor (JLT) has been studied experimentally and theoretically. JLT showed less mobility degradation compared to the inversion-mode transistor in both planar-like and nanowire structures. The unique transconductance shape and the reduced degradation of the mobility in the nanowire JLT showed that it still has bulk neutral conduction portion in its total conduction while the immunity to the mobility degradation of JLT is enhanced with planar-structure. 2-dimensional numerical simulation confirmed the reduced transverse electric-field with bulk neutral conduction in JLT as well as the deviation of transconductance degradation by the channel doping concentration and the channel top width.
    Applied Physics Letters 11/2014; 105(21):213504. DOI:10.1063/1.4902549 · 3.52 Impact Factor
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    ABSTRACT: gate nanowires (NW) P-FETs on compressively-strained– SiGe-on-insulator (cSGOI) substrate obtained by the Ge enrichment technique are presented. Effectiveness of cSGOI channel is demonstrated for ultra-scaled P-FET NW (LG=15nm and WNW=25nm) with an outstanding ION current (ION=860µA/µm at IOFF=140nA/µm) and a good electrostatics immunity (DIBL=110mV/V). For the first time, Si0.8Ge0.2– channel transistors highlight a mobility improvement for narrow NWs down to short gate length compared to Si one (92% for LG=30nm). The hole mobility improvement provided by the strong uniaxial compressive strain coming from cSiGe and cCESL leads to an ION current improvement of 95% at LG=15nm.
    IEEE S3S 2014 Conference, San Francisco Aeroport; 10/2014
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    ABSTRACT: We have developed an innovative 500 degrees C process for the selective deposition of SiGe:B Raised Sources and Drains (RSDs). We have first of all studied on blanket Si wafers the in-situ boron doping of SiGe with Si2H6, GeH4 and B2H6. A growth rate increase by a factor higher than 4 together with a Ge concentration decrease from 45% down to 28% occurred as the diborane mass-flow increased (at 500 degrees C, 20 Torr). Very high substitutional boron concentrations were achieved (similar to 5 x 10(20) cm(-3)) in layers that were single crystalline and flat. Adding large amounts of HCl to the gaseous mixture did not yield the selectivity aimed for on SiO2-covered Si wafers, however. To that end, we have thus benchmarked various 500 degrees C Cyclic Deposition / Etch (CDE) processes. 12 cycles CDE processes were characterized by HCl etch rates of poly-SiGe:B that were too low to be of any practical use or yielded 3 dimensional SiGe: B layers on Si(001). Straightforward Deposition / Etch (DE) processes, with the HCl selective etch of poly-SiGe: B carried out at 740 Torr (i.e. atmospheric pressure), enabled us by contrast to achieve selectivity on SiO2 while retaining single crystalline and slightly rough SiGe: B layers. Those DE processes were tested on patterned Silicon-On-Insulator substrates with gate stacks. Longer HCl etch times than the ones identified on blanket wafers were key in getting rid of poly-SiGe: B on top of dielectrics covered surfaces; rather smooth, facetted SiGe: B RSDs were obtained in the end.
    09/2014; 3(11):P382-P390. DOI:10.1149/2.0161411jss
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    ABSTRACT: We investigate the impact of performance boosters using mechanical stress on the Single-Event Transient (SET) response of nanometer scaled Fully-Depleted Silicon-On-Insulator (SOI) devices. Laser SET measurements show that the active silicon layer thickness is the most important contributor to the SET response of highly scaled Ultra-Thin SOI (UTSOI) devices compared to the impact of strain. This is then demonstrated by dedicated TCAD calculations performed without taking into account any strain engineering technique. Finally, heavy ion-induced charge collection mechanisms are analyzed through the measurement of fast transients to get additional insights into the impact of short channel effects on the SET response of nanometer scaled SOI devices.
    IEEE Transactions on Nuclear Science 08/2014; 61(4):1628-1634. DOI:10.1109/TNS.2014.2314143 · 1.46 Impact Factor
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    ABSTRACT: We present the co-integration of a ring-oscillator based CMOS circuit purposely designed to drive RF signals onto the gates of a single-electron device. It is fabricated on 300 mm wafers with the nanowire silicon-on-insulator technology and operated at cryogenic temperatures. Using the same technology for both the classical circuit and the quantum device is a unique opportunity which is implemented by simply changing the width of the field-effect transistors. While 25 nm widths yield devices behaving as quantum devices, 1μm relaxed widths guarantee a safe operation of the CMOS circuit since its components behave as regular Field-Effect transistors. We demonstrate the operation of the circuit at low temperature and observed the generation of DC currents in the absence of any applied DC bias. The generated DC current can be well explained in the framework of a rectification model [8]. The successful operation of such a co-integrated circuit can be very promising for future integration of quantum nanoelectronic devices.
    2014 11th International Workshop on Low Temperature Electronics (WOLTE); 07/2014
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    ABSTRACT: The Hall and effective mobility characteristics of n-type junctionless transistors (JLTs) at low temperature (T=100K) are reported here for the first time. To this end, the effective mobility values (μEff) were extracted from the charge based analytical model of JLT with account for flat-band (VFB) position and split capacitance-to-voltage (CV), respectively. Besides, in order to directly determine the surface carrier density (Ns) and corresponding Hall mobility (μHall) Hall Effect measurements were carried out and compared to μEff.
    2014 11th International Workshop on Low Temperature Electronics (WOLTE); 07/2014
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    ABSTRACT: The error rate of low-field mobility (μ0) extracted from the conventional Y-function method in junctionless transistors (JLTs) is found to be linearly proportional to the channel doping concentration (Nd) for a typical value of the first order mobility attenuation factor θ0 ≈ 0.1 V−1. Therefore, for a better understanding of their physical operation with higher accuracy, a methodology for the extraction of the low-field mobility of the surface accumulation channel (μ0_acc) and the bulk neutral channel mobility (μbulk) of JLTs is proposed based on their unique operation principle. Interestingly, it is found that the different temperature dependence between μ0_acc and μbulk is also confirming that the distribution of point defects along the channel in the heavily doped Si channel of JLTs was non-uniform.
    Applied Physics Letters 06/2014; 104(26):263510-263510-5. DOI:10.1063/1.4886139 · 3.52 Impact Factor
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    ABSTRACT: The continuous downscaling of transistors results in nanoscale devices which require fewer and fewer charged carriers for their operation. The ultimate charge controlled device, the single-electron transistor (SET), controls the transfer of individual electrons. It is also the most sensitive electrometer, and as a result the electron transport through it can be dramatically affected by nearby charges. Standard direct-current characterization techniques, however, are often unable to unambiguously detect and resolve the origin of the observed changes in SET behavior arising from changes in the charge state of a capacitively coupled trap. Using a radio-frequency (RF) reflectometry technique, we are able to unequivocally detect this process, in very close agreement with modeling of the trap's occupation probability.
    Applied Physics Letters 06/2014; 104(23):233503-233503-4. DOI:10.1063/1.4883228 · 3.52 Impact Factor

Publication Stats

531 Citations
175.80 Total Impact Points

Institutions

  • 2006–2015
    • Cea Leti
      Grenoble, Rhône-Alpes, France
  • 2014
    • University of Grenoble
      Grenoble, Rhône-Alpes, France
  • 2008–2014
    • Atomic Energy and Alternative Energies Commission
      Fontenay, Île-de-France, France
  • 2013
    • Korea University
      • Department of Electrical Engineering
      Sŏul, Seoul, South Korea
  • 2000–2006
    • Université Paris-Sud 11
      • Institut d'Electronique Fondamentale
      Orsay, Île-de-France, France
  • 2004
    • Institute of Fundamental Electronics
      Orsay, Île-de-France, France
  • 2002
    • French National Centre for Scientific Research
      Lutetia Parisorum, Île-de-France, France