S. Barraud

Atomic Energy and Alternative Energies Commission, Fontenay, Île-de-France, France

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Publications (113)126.39 Total impact

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    ABSTRACT: uantum computation requires a qubit-specific measurement capability to readout the final state of individual qubits. Promising solid-state architectures use external readout electrometers but these can be replaced by a more compact readout element, an in situ gate sensor. Gate-sensing couples the qubit to a resonant circuit via a gate and probes the qubit’s radiofrequency polarizability. Here we investigate the ultimate performance of such a resonant readout scheme and the noise sources that limit its operation. We find a charge sensitivity of 37 μe Hz−1/2, the best value reported for this technique, using the example of a gate sensor strongly coupled to a double quantum dot at the corner states of a silicon nanowire transistor. We discuss the experimental factors limiting gate detection and highlight ways to optimize its sensitivity. In total, resonant gate-based readout has advantages over external electrometers both in terms of reduction of circuit elements as well as absolute charge sensitivity.
    Nature Communications 01/2015; 6:6084. · 10.74 Impact Factor
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    ABSTRACT: gate nanowires (NW) P-FETs on compressively-strained– SiGe-on-insulator (cSGOI) substrate obtained by the Ge enrichment technique are presented. Effectiveness of cSGOI channel is demonstrated for ultra-scaled P-FET NW (LG=15nm and WNW=25nm) with an outstanding ION current (ION=860µA/µm at IOFF=140nA/µm) and a good electrostatics immunity (DIBL=110mV/V). For the first time, Si0.8Ge0.2– channel transistors highlight a mobility improvement for narrow NWs down to short gate length compared to Si one (92% for LG=30nm). The hole mobility improvement provided by the strong uniaxial compressive strain coming from cSiGe and cCESL leads to an ION current improvement of 95% at LG=15nm.
    IEEE S3S 2014 Conference, San Francisco Aeroport; 10/2014
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    IEEE Transactions on Nuclear Science 08/2014; 61(4):1628-1634. · 1.46 Impact Factor
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    ABSTRACT: The Hall and effective mobility characteristics of n-type junctionless transistors (JLTs) at low temperature (T=100K) are reported here for the first time. To this end, the effective mobility values (μEff) were extracted from the charge based analytical model of JLT with account for flat-band (VFB) position and split capacitance-to-voltage (CV), respectively. Besides, in order to directly determine the surface carrier density (Ns) and corresponding Hall mobility (μHall) Hall Effect measurements were carried out and compared to μEff.
    2014 11th International Workshop on Low Temperature Electronics (WOLTE); 07/2014
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    ABSTRACT: We present the co-integration of a ring-oscillator based CMOS circuit purposely designed to drive RF signals onto the gates of a single-electron device. It is fabricated on 300 mm wafers with the nanowire silicon-on-insulator technology and operated at cryogenic temperatures. Using the same technology for both the classical circuit and the quantum device is a unique opportunity which is implemented by simply changing the width of the field-effect transistors. While 25 nm widths yield devices behaving as quantum devices, 1μm relaxed widths guarantee a safe operation of the CMOS circuit since its components behave as regular Field-Effect transistors. We demonstrate the operation of the circuit at low temperature and observed the generation of DC currents in the absence of any applied DC bias. The generated DC current can be well explained in the framework of a rectification model [8]. The successful operation of such a co-integrated circuit can be very promising for future integration of quantum nanoelectronic devices.
    2014 11th International Workshop on Low Temperature Electronics (WOLTE); 07/2014
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    ABSTRACT: The error rate of low-field mobility (μ0) extracted from the conventional Y-function method in junctionless transistors (JLTs) is found to be linearly proportional to the channel doping concentration (Nd) for a typical value of the first order mobility attenuation factor θ0 ≈ 0.1 V−1. Therefore, for a better understanding of their physical operation with higher accuracy, a methodology for the extraction of the low-field mobility of the surface accumulation channel (μ0_acc) and the bulk neutral channel mobility (μbulk) of JLTs is proposed based on their unique operation principle. Interestingly, it is found that the different temperature dependence between μ0_acc and μbulk is also confirming that the distribution of point defects along the channel in the heavily doped Si channel of JLTs was non-uniform.
    Applied Physics Letters 06/2014; 104(26):263510-263510-5. · 3.52 Impact Factor
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    ABSTRACT: The continuous downscaling of transistors results in nanoscale devices which require fewer and fewer charged carriers for their operation. The ultimate charge controlled device, the single-electron transistor (SET), controls the transfer of individual electrons. It is also the most sensitive electrometer, and as a result the electron transport through it can be dramatically affected by nearby charges. Standard direct-current characterization techniques, however, are often unable to unambiguously detect and resolve the origin of the observed changes in SET behavior arising from changes in the charge state of a capacitively coupled trap. Using a radio-frequency (RF) reflectometry technique, we are able to unequivocally detect this process, in very close agreement with modeling of the trap's occupation probability.
    Applied Physics Letters 06/2014; 104(23):233503-233503-4. · 3.52 Impact Factor
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    ABSTRACT: Si CMOS single-electron transistors (SET) fabricated using fully depleted SOI [1] enable an understanding of charging mechanisms in ultimately scaled CMOS devices down to a transport through a single dopant [2]. A schematic representation of such a device is shown in Fig 1. Radio-frequency (RF) reflectometry [3] is an effective tool for charge detection in various single-electron systems. Since it does not require any DC current flow the detection of electrons passing even through a single tunnel junction [4] is possible. When a Si SET is populated with electrons, one intriguing question need to be answered: where do the first charge carriers spatially accumulate during the formation of the conducting “island”? To address this issue we use a dual channel technique that enables spatial identification of charging processes within the device. Here we present results obtained using this technique for single-hole transistors (SHT). A micrograph of a typical studied SHT device.
    2014 72nd Annual Device Research Conference (DRC); 06/2014
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    ABSTRACT: The implementation of a quantum computer requires a qubit-specific measurement capability to read-out the final state of a quantum system. The model of spin dependent tunneling followed by charge readout has been highly successful in enabling spin qubit experiments in all-electrical, semiconductor based quantum computing. As experiments grow more sophisticated, and head towards multiple qubit architectures that enable small scale computation, it becomes important to consider the charge read-out overhead. With this in mind, Reilly et al. demonstrated a gate readout scheme in a GaAs double quantum dot that removed the need for an external charge sensor. This readout, which achieved sensitivities of order me/$\sqrt(Hz)$, was enabled by using a resonant circuit to probe the complex radio-frequency polarisability of the double quantum dot. However, the ultimate performance of this technology and the noise sources that limit it remain to be determined. Here, we investigate a gate-based readout scheme using a radio-frequency resonant circuit strongly coupled to a double quantum at the corner states of a silicon nanowire transistor. We find a significantly improved charge sensitivity of 37 $\mu$e/$\sqrt(Hz)$. By solving the dynamical master equation of the fast-driven electronic transitions we quantify the noise spectral density and determine the ultimate charge and phase sensitivity of gate-based read-out. We find comparable performance to conventional charge sensors and fundamental limits of order ne/$\sqrt(Hz)$ and $\mu$rad/$\sqrt(Hz)$, with the gate-based sensor improving on standard detection for certain device parameters. Our results show that, especially in state-of-the-art silicon qubit architectures, charge detection by probing the complex polarisability has advantages in terms of reducing the readout overhead but also in terms of the absolute charge sensitivity.
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    ABSTRACT: We review in this paper some key enabling process integration modules, the development of which will allow pursuing the trend of energy efficiency improvement in sub-28nm FDSOI technologies.
    2014 14th International Workshop on Junction Technology (IWJT); 05/2014
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    ABSTRACT: A study of the interface quality in ultra-scaled omega-gate nanowire NMOSFETs, with variant technological boosters, is presented by low-frequency noise (LFN) measurements. Excellent quality of the interfaces has been achieved down to narrow width (10nm), and whatever the technological splits. In particular, efficient tensile stressor has been demonstrated with high performance enhancement and preserved noise performance fulfilling the ITRS 1/f LFN road map.
    2014 International Symposium on VLSI Technology, Systems and Application (VLSI-TSA); 04/2014
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    ABSTRACT: Short-gate length epitaxial ${rm Si}_{1-x}{rm Ge}_{x}/{rm Si}$ multi-(core/shell) p-type nanowire (NW) transistors with high-permittivity dielectric and metal gate were fabricated and their electrical properties examined. Silicon NWs were first of all patterned in ultrathin silicon-on-insulator wafers by lithography and etching. Selective epitaxial growth of ${rm Si}_{0.7}{rm Ge}_{0.3}/{rm Si}$ or ${rm Si}_{0.7}{rm Ge}_{0.3}/{rm Si}/{rm Si}_{0.7}{rm Ge}_{0.3}/{rm Si}$ shells was then performed around the Si NW core. Electrical transport measurements showed a hole mobility improvement up to 100% in ${rm Si}_{0.7}{rm Ge}_{0.3}/{rm Si}/{rm Si}_{0.7}{rm Ge}_{0.3}/{rm Si}$ core/shell NWs (70% in wide planar devices) compared with p-type Si reference field effect transistors (FETs). Finally, a drive current enhancement of 60% compared with reference Si-channel devices was evidenced in multi-(core/shell) p-FET NWs scaled down to 15-nm gate length.
    IEEE Transactions on Electron Devices 04/2014; 61(4):953-956. · 2.36 Impact Factor
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    ABSTRACT: High-performance strained Silicon-On-Insulator (sSOI) nanowire (NW) transistors with gate length and NW width down to 15 nm are reported. We demonstrate sSOI π-Gate n-FET NWs with ION current of 1410 μA/μm (when IOFF = 70 nA/μm) at VDD=0.9V and a good electrostatic immunity (DIBL = 140 mV/V, SSSAT = 76 mV/dec). Effectiveness of sSOI substrates for n-FETs is shown with an ION improvement up to +40% at short gate lengths. More generally, size- and orientation-dependent strain impact on electron and hole transport in long and short channel π-Gate (s)SOI NW transistors is systematically studied.
    2014 15th International Conference on Ultimate Integration on Silicon (ULIS); 04/2014
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    ABSTRACT: We investigate the gate-induced onset of few-electron regime through the undoped channel of a silicon nanowire field-effect transistor. By combining low-temperature transport measurements and self-consistent calculations, we reveal the formation of one-dimensional conduction modes localized at the two upper edges of the channel. Charge traps in the gate dielectric cause electron localization along these edge modes, creating elongated quantum dots with characteristic lengths of $\sim10$ nm. We observe single-electron tunneling across two such dots in parallel, specifically one in each channel edge. We identify the filling of these quantum dots with the first few electrons, measuring addition energies of a few tens of meV and level spacings of the order of 1 meV, which we ascribe to the valley orbit splitting. The total removal of valley degeneracy leaves only a two-fold spin degeneracy, making edge quantum dots potentially promising candidates for silicon spin qubits.
    Nano Letters 03/2014; 14(4):2094. · 13.03 Impact Factor
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    ABSTRACT: This paper presents the low-temperature characteristics of flat-band (VFB) and low-field mobility in accumulation regime (µ0_acc) of n-type junctionless transistors (JLTs). To this end, split capacitance-to-voltage (C–V), dual gate coupling and low-temperature measurements were carried out to systematically investigate VFB. Additionally, the gate oxide capacitance per unit area Cox and the doping concentration ND were evaluated as well. Accounting for the position of VFB and the charge based analytical model of JLTs, bulk mobility (µB) and µ0_acc were separately extracted in volume and surface conduction regime, respectively. Finally, the role of neutral scattering defects was found the most limiting factor concerning the degradation of µB and µ0_acc with gate length in planar and tri-gate nanowire JLTs.
    Semiconductor Science and Technology 03/2014; 29(4):045024. · 2.21 Impact Factor
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    ABSTRACT: For 11nm and below, several alternatives are still potential candidates to meet the patterning requirements. Spacer patterning, Mask Less Lithography (i.e. Electron beam lithography) and Direct Self Assembly are alternatives under development at CEA-LETI. We have demonstrated the integration of these alternative techniques in front end of line and back end of line levels. Common challenges such as minimum achievable CD, CD control through the integration steps, mask budget and LWR were compared for these techniques.
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    ABSTRACT: The impact of channel width on back biasing effect in n-type tri-gate metal-oxide semiconductor field effect transistor (MOSFET) on silicon-on-insulator (SOI) material was investigated. In narrow device (Wtop_eff = 20 nm), the relatively high control of front gate on overall channel leads to the reduced electrostatic coupling between back and front channels as well as the suppression of back bias effects on both channel threshold voltage and the effective mobility, compared to the planar device (Wtop_eff = 170 nm). The lower effective mobility with back bias in narrow device was attributed to poorer front channel interface, and, to significant effect of sidewall mobility. The back biasing effect in tri-gate MOSFET was successfully modeled with 2-D numerical simulation. Through the simulation, the mobility results were interpreted as the consequence of two kinds of mobility degradations, i.e. different mobility attenuation along lateral and vertical directions of channel and additional mobility degradation in narrow device due to the effect of sidewall mobility. The potential profile extracted from numerical simulation provides strong evidence showing different degree of electrostatic coupling in narrow device and planar device due to a relative influence of front gate bias control over channels.
    Microelectronic Engineering 02/2014; 114:91–97. · 1.34 Impact Factor
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    ABSTRACT: We report on DC and microwave electrical transport measurements in silicon-on-insulator nano-transistors at low and room temperature. At low source-drain voltage, the DC current and radio frequency response show signs of conductance quantization. We attribute this to Coulomb blockade resulting from barriers formed at the spacer-gate interfaces. We show that at high bias transport occurs thermionically over the highest barrier: Transconductance traces obtained from microwave scattering-parameter measurements at liquid helium and room temperature are accurately fitted by a thermionic model. From the fits we deduce the ratio of gate capacitance and quantum capacitance, as well as the electron temperature.
    Applied Physics Letters 01/2014; 104(4):043106-043106-4. · 3.52 Impact Factor
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    ABSTRACT: Several electrical parameters characterize device performance, electron transport and doping level in MOS transistors. In this paper, Junctionless Transistors (JLTs) fabricated on (100) silicon on insulator (SOI) wafer with 145 nm thick BOX and 9 nm silicon thickness were considered. Parameter extraction methodologies were revisited in order to account for the unique electrical properties of JLT devices. The deduced parameters, such as threshold voltage, flat-band voltage, drain induced barrier lowering (DIBL), low field mobility and channel doping level, are shown to reveal the specific features of JLT compared to conventional inversion-mode transistors.
    Solid-State Electronics 12/2013; 90:86–93. · 1.51 Impact Factor

Publication Stats

310 Citations
126.39 Total Impact Points


  • 2010–2014
    • Atomic Energy and Alternative Energies Commission
      Fontenay, Île-de-France, France
  • 2005–2014
    • Cea Leti
      Grenoble, Rhône-Alpes, France
  • 2013
    • Korea University
      • Department of Electrical Engineering
      Sŏul, Seoul, South Korea
  • 2004
    • Institute of Fundamental Electronics
      Orsay, Île-de-France, France
  • 2000–2002
    • Université Paris-Sud 11
      • Institut d'Electronique Fondamentale
      Paris, Ile-de-France, France