S. Barraud

Atomic Energy and Alternative Energies Commission, Gif, Île-de-France, France

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Publications (99)104.18 Total impact

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    ABSTRACT: The implementation of a quantum computer requires a qubit-specific measurement capability to read-out the final state of a quantum system. The model of spin dependent tunneling followed by charge readout has been highly successful in enabling spin qubit experiments in all-electrical, semiconductor based quantum computing. As experiments grow more sophisticated, and head towards multiple qubit architectures that enable small scale computation, it becomes important to consider the charge read-out overhead. With this in mind, Reilly et al. demonstrated a gate readout scheme in a GaAs double quantum dot that removed the need for an external charge sensor. This readout, which achieved sensitivities of order me/$\sqrt(Hz)$, was enabled by using a resonant circuit to probe the complex radio-frequency polarisability of the double quantum dot. However, the ultimate performance of this technology and the noise sources that limit it remain to be determined. Here, we investigate a gate-based readout scheme using a radio-frequency resonant circuit strongly coupled to a double quantum at the corner states of a silicon nanowire transistor. We find a significantly improved charge sensitivity of 37 $\mu$e/$\sqrt(Hz)$. By solving the dynamical master equation of the fast-driven electronic transitions we quantify the noise spectral density and determine the ultimate charge and phase sensitivity of gate-based read-out. We find comparable performance to conventional charge sensors and fundamental limits of order ne/$\sqrt(Hz)$ and $\mu$rad/$\sqrt(Hz)$, with the gate-based sensor improving on standard detection for certain device parameters. Our results show that, especially in state-of-the-art silicon qubit architectures, charge detection by probing the complex polarisability has advantages in terms of reducing the readout overhead but also in terms of the absolute charge sensitivity.
    05/2014;
  • 04/2014;
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    ABSTRACT: We investigate the gate-induced onset of few-electron regime through the undoped channel of a silicon nanowire field-effect transistor. By combining low-temperature transport measurements and self-consistent calculations, we reveal the formation of one-dimensional conduction modes localized at the two upper edges of the channel. Charge traps in the gate dielectric cause electron localization along these edge modes, creating elongated quantum dots with characteristic lengths of $\sim10$ nm. We observe single-electron tunneling across two such dots in parallel, specifically one in each channel edge. We identify the filling of these quantum dots with the first few electrons, measuring addition energies of a few tens of meV and level spacings of the order of 1 meV, which we ascribe to the valley orbit splitting. The total removal of valley degeneracy leaves only a two-fold spin degeneracy, making edge quantum dots potentially promising candidates for silicon spin qubits.
    Nano Letters 03/2014; 14(4):2094. · 13.03 Impact Factor
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    ABSTRACT: This paper presents the low-temperature characteristics of flat-band (VFB) and low-field mobility in accumulation regime (µ0_acc) of n-type junctionless transistors (JLTs). To this end, split capacitance-to-voltage (C–V), dual gate coupling and low-temperature measurements were carried out to systematically investigate VFB. Additionally, the gate oxide capacitance per unit area Cox and the doping concentration ND were evaluated as well. Accounting for the position of VFB and the charge based analytical model of JLTs, bulk mobility (µB) and µ0_acc were separately extracted in volume and surface conduction regime, respectively. Finally, the role of neutral scattering defects was found the most limiting factor concerning the degradation of µB and µ0_acc with gate length in planar and tri-gate nanowire JLTs.
    Semiconductor Science and Technology 03/2014; 29(4):045024. · 1.92 Impact Factor
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    ABSTRACT: For 11nm and below, several alternatives are still potential candidates to meet the patterning requirements. Spacer patterning, Mask Less Lithography (i.e. Electron beam lithography) and Direct Self Assembly are alternatives under development at CEA-LETI. We have demonstrated the integration of these alternative techniques in front end of line and back end of line levels. Common challenges such as minimum achievable CD, CD control through the integration steps, mask budget and LWR were compared for these techniques.
    02/2014;
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    ABSTRACT: The impact of channel width on back biasing effect in n-type tri-gate metal-oxide semiconductor field effect transistor (MOSFET) on silicon-on-insulator (SOI) material was investigated. In narrow device (Wtop_eff = 20 nm), the relatively high control of front gate on overall channel leads to the reduced electrostatic coupling between back and front channels as well as the suppression of back bias effects on both channel threshold voltage and the effective mobility, compared to the planar device (Wtop_eff = 170 nm). The lower effective mobility with back bias in narrow device was attributed to poorer front channel interface, and, to significant effect of sidewall mobility. The back biasing effect in tri-gate MOSFET was successfully modeled with 2-D numerical simulation. Through the simulation, the mobility results were interpreted as the consequence of two kinds of mobility degradations, i.e. different mobility attenuation along lateral and vertical directions of channel and additional mobility degradation in narrow device due to the effect of sidewall mobility. The potential profile extracted from numerical simulation provides strong evidence showing different degree of electrostatic coupling in narrow device and planar device due to a relative influence of front gate bias control over channels.
    Microelectronic Engineering 01/2014; 114:91–97. · 1.22 Impact Factor
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    ABSTRACT: The error rate of low-field mobility (μ0) extracted from the conventional Y-function method in junctionless transistors (JLTs) is found to be linearly proportional to the channel doping concentration (Nd) for a typical value of the first order mobility attenuation factor θ0 ≈ 0.1 V−1. Therefore, for a better understanding of their physical operation with higher accuracy, a methodology for the extraction of the low-field mobility of the surface accumulation channel (μ0_acc) and the bulk neutral channel mobility (μbulk) of JLTs is proposed based on their unique operation principle. Interestingly, it is found that the different temperature dependence between μ0_acc and μbulk is also confirming that the distribution of point defects along the channel in the heavily doped Si channel of JLTs was non-uniform.
    Applied Physics Letters 01/2014; 104(26):263510-263510-5. · 3.79 Impact Factor
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    ABSTRACT: Short-gate length epitaxial ${rm Si}_{1-x}{rm Ge}_{x}/{rm Si}$ multi-(core/shell) p-type nanowire (NW) transistors with high-permittivity dielectric and metal gate were fabricated and their electrical properties examined. Silicon NWs were first of all patterned in ultrathin silicon-on-insulator wafers by lithography and etching. Selective epitaxial growth of ${rm Si}_{0.7}{rm Ge}_{0.3}/{rm Si}$ or ${rm Si}_{0.7}{rm Ge}_{0.3}/{rm Si}/{rm Si}_{0.7}{rm Ge}_{0.3}/{rm Si}$ shells was then performed around the Si NW core. Electrical transport measurements showed a hole mobility improvement up to 100% in ${rm Si}_{0.7}{rm Ge}_{0.3}/{rm Si}/{rm Si}_{0.7}{rm Ge}_{0.3}/{rm Si}$ core/shell NWs (70% in wide planar devices) compared with p-type Si reference field effect transistors (FETs). Finally, a drive current enhancement of 60% compared with reference Si-channel devices was evidenced in multi-(core/shell) p-FET NWs scaled down to 15-nm gate length.
    IEEE Transactions on Electron Devices 01/2014; 61(4):953-956. · 2.06 Impact Factor
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    ABSTRACT: The continuous downscaling of transistors results in nanoscale devices which require fewer and fewer charged carriers for their operation. The ultimate charge controlled device, the single-electron transistor (SET), controls the transfer of individual electrons. It is also the most sensitive electrometer, and as a result the electron transport through it can be dramatically affected by nearby charges. Standard direct-current characterization techniques, however, are often unable to unambiguously detect and resolve the origin of the observed changes in SET behavior arising from changes in the charge state of a capacitively coupled trap. Using a radio-frequency (RF) reflectometry technique, we are able to unequivocally detect this process, in very close agreement with modeling of the trap's occupation probability.
    Applied Physics Letters 01/2014; 104(23):233503-233503-4. · 3.79 Impact Factor
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    ABSTRACT: We report on DC and microwave electrical transport measurements in silicon-on-insulator nano-transistors at low and room temperature. At low source-drain voltage, the DC current and radio frequency response show signs of conductance quantization. We attribute this to Coulomb blockade resulting from barriers formed at the spacer-gate interfaces. We show that at high bias transport occurs thermionically over the highest barrier: Transconductance traces obtained from microwave scattering-parameter measurements at liquid helium and room temperature are accurately fitted by a thermionic model. From the fits we deduce the ratio of gate capacitance and quantum capacitance, as well as the electron temperature.
    Applied Physics Letters 01/2014; 104(4):043106-043106-4. · 3.79 Impact Factor
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    ABSTRACT: We report on DC and microwave electrical transport measurements in silicon-on-insulator CMOS nano-transistors at low and room temperature. At low source-drain voltage, the DC current and RF response show signs of conductance quantization. We attribute this to Coulomb blockade resulting from barriers formed at the spacer-gate interfaces. We show that at high bias transport occurs thermionically over the highest barrier: Transconductance traces obtained from microwave scattering-parameter measurements at liquid helium and room temperature is accurately fitted by a thermionic model. From the fits we deduce the ratio of gate capacitance and quantum capacitance, as well as the electron temperature.
    12/2013;
  • Solid-State Electronics 11/2013; · 1.48 Impact Factor
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    ABSTRACT: The structural and chemical properties of advanced nano-devices with a three-dimensional (3D) architecture have been studied at the nanometre scale. An original method has been used to characterize gate-all-around and tri-gate silicon nanowire transistor by combining electron tomography and atom probe tomography (APT). Results show that electron tomography is a well suited method to determine the morphological structure and the dimension variations of devices provided that the atomic number contrast is sufficient but without an absolute chemical identification. APT can map the 3D chemical distribution of the atoms in devices but suffers from strong distortions in the dimensions of the reconstructed volume. These may be corrected using a simple method based on atomic density correction and electron tomography data. Moreover, this combination is particularly useful in helping to understand the evaporation mechanisms and improve APT reconstructions. This paper demonstrated that a full 3D characterization of nano-devices requires the combination of both tomography techniques.
    Ultramicroscopy 10/2013; 136C:185-192. · 2.47 Impact Factor
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    ABSTRACT: The performance of semiconductor devices can be linked to geometry and variations of the structure. For transistors in particular, the geometry of the gate stack is essential. In this work we investigate the gate stack of a tri-gate transistor using dual-axis electron tomography. This allows the reconstruction of all surfaces of the gate of the transistor with high resolution and measurement of the local thickness of the gate oxide. While previously, dual-axis electron tomography was employed for reducing missing wedge artifacts, our work demonstrates the potential of dual-axis tomography for improving the resolution of a tomographic reconstruction, even for structures not affected by missing wedge artifacts. By simulations and experiments we show the value of dual-axis tomography for characterization of nanoscale devices as an approach that requires no prior information and that can be easily extended even to more than two tilt axes.
    Ultramicroscopy 10/2013; 136C:144-153. · 2.47 Impact Factor
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    ABSTRACT: Ultrashort gate length silicon-on-insulator nanowire (NW) transistors with embedded source/drain (S/D) SiGe stressors were fabricated. An enhancement of P-FET NW performance is achieved using in situ HCl+GeH4 etching and selective epitaxial growth of boron-doped Si0.7Ge0.3 for the formation of recessed S/D. For the first time, an ION current improvement of +100% along the 〈110〉 direction induced by SiGe S/D is achieved in Omega-FET NWs down to 13-nm gate length. The current enhancement coming from uniaxial compressive strain of recessed SiGe S/D stressors in narrow-channel transistors is well demonstrated (+100% versus +40% in wide planar FET).
    IEEE Electron Device Letters 09/2013; 34(9):1103-1105. · 2.79 Impact Factor
  • Solid-State Electronics 09/2013; · 1.48 Impact Factor
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    ABSTRACT: We report an experimental study of the carrier transport in [1 1 0]-oriented long channel tri-gate (TG) and omega-gate (ΩG) silicon nanowire (SiNW) transistors cross-section down to 11 nm × 10 nm. Electron and hole mobilities have been measured down to 20 K to evaluate the contribution from the dominant scattering mechanisms. We have studied and discussed the influence of channel shape, channel width and strain effect on carrier mobility. In particular, we have shown that the transport properties are mainly driven by the relative contribution of the different inversion surfaces, without noticeable differences between TG and ΩGNWs. We have also demonstrated the effectiveness of an additional uniaxial tensile strain in NMOS NWs down to 10 nm width.
    Solid-State Electronics 06/2013; 84:46–52. · 1.48 Impact Factor
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    ABSTRACT: In this paper we show that on scaling nanowire width from 20 nm down to sub-7 nm regime, together with achieving excellent short channel effect control (DIBL = 12 mV/V for LG = 20 nm), we hit a dramatic transition in transport mechanism from monotonously increasing ID–VG of a FET to oscillating ID–VG of a Single Electron Transistor. This transition in transport mechanism is brought about by process induced channel potential variability. It poses a challenge to further scaling of nanowire MOSFETs. However, we show that it provides an exciting opportunity to cointegrate Single Electron Transistors with high-k/metal gate operating at room temperature (at VD = ±0.9 V) with the state-of-the-art nanowire MOSFETs enabling large scale manufacturing of Beyond Moore devices.
    Solid-State Electronics 06/2013; 84:179–184. · 1.48 Impact Factor
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    ABSTRACT: The sidewall mobility and the series resistance in a multichannel tri-gate MOSFET were examined with low-temperature measurement and 2D numerical simulation. With sidewall mobility separated from total transfer characteristics, it was shown that the sidewall conduction is mainly affected by the surface roughness scattering. The effect of surface roughness scattering on sidewall mobility was evaluated with the mobility degradation factor normalized by the low field mobility, which exhibited an almost six times higher value than that of top surface mobility. The series resistance of the multichannel tri-gate MOSFET was studied by comparing with that of the planar MOSFET. Through 2D numerical simulation, it was revealed that relatively high series resistance of the multichannel tri-gate MOSFET is attributed to the variation of doping concentration in the source/drain extension region in the device.
    Semiconductor Science and Technology 05/2013; 28(6):065009. · 1.92 Impact Factor
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    ABSTRACT: Low-frequency (LF) noise characteristics of wide planar junctionless transistors (JLTs) are investigated. Interestingly, carrier number fluctuation is the main contributor to the LF noise behavior of JLT devices, even though their bulk conduction features are clearly proved by the extracted flat-band voltage (Vfb). This is explained by the fact that mobile electrons in depletion, originating from the bulk neutral channel or source/drain regions, can interact with slow traps in the gate oxide, giving rise in return to fluctuations of the charge density in the bulk neutral channel. Similar values of trap density (Nt) are extracted in JLT devices and inversion-mode (IM) t0072ansistors, which also supports that the LF noise of JLT is well explained by the carrier number fluctuation model.
    Solid-State Electronics 03/2013; 81:101–104. · 1.48 Impact Factor

Publication Stats

232 Citations
104.18 Total Impact Points

Institutions

  • 2010–2014
    • Atomic Energy and Alternative Energies Commission
      Gif, Île-de-France, France
  • 2005–2014
    • Cea Leti
      Grenoble, Rhône-Alpes, France
  • 2013
    • Korea University
      • Department of Electrical Engineering
      Sŏul, Seoul, South Korea
  • 2004
    • Institute of Fundamental Electronics
      Orsay, Île-de-France, France
  • 2000–2002
    • Université Paris-Sud 11
      • Institut d'Electronique Fondamentale
      Paris, Ile-de-France, France