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ABSTRACT: The strengths of Cu-bonded wafers with respect to different bonding temperatures and bonding durations by quantitative and
qualitative approaches were reviewed and investigated. These investigations include the mechanical dicing test, the tape test,
the pull test, and the push test. For all test results, the strength of Cu-bonded wafers increases with increases in bonding
duration or bonding temperature. Thermal anneal after bonding improved the bonding strength only at the high bonding temperature
and not at the low temperature.
Journal of Electronic Materials 04/2006; 35(5):1082-1086. · 1.47 Impact Factor
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ABSTRACT: A reliable copper wafer bonding process condition, which provides strong bonding at low bonding temperature with a short bonding
duration and does not affect the device structure, is desirable for future three-dimensional (3-D) integration applications.
In this review paper, the effects of different process parameters on the quality of blanket copper wafer bonding are reviewed
and summarized. An overall view of copper wafer bonding for different bonding parameters, including pressure, temperature,
duration, clean techniques, and anneal option, can be established. To achieve excellent copper wafer bonding results, 400°C
bonding for 30 min. followed by 30 min. nitrogen anneal or 350°C bonding for 30 min. followed by 60 min. anneal bonding is
necessary. In addition, by meeting the process requirements of future integrated circuit (IC) processes, the best bonding
condition for 3-D integration can be determined.
Journal of Electronic Materials 01/2006; 35(2):230-234. · 1.47 Impact Factor
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ABSTRACT: In order to achieve copper wafer bonding with good quality, surface conditions of copper films are important factors. In this
work, the effects of surface conditions, such as surface roughness and oxide formation on the bond strength, were investigated
under different bonding conditions. Prior to bonding, copper film surfaces were kept in the atmosphere for less than 1 min,
3 days, and 7 days, respectively, to form different thicknesses of oxide on the surface. Some copper wafers were cleaned using
HCl before bonding in order to remove the surface oxide. Surface roughness of copper films with and without HCl cleaning was
examined. Since surface cleaning before bonding removes oxides but creates surface roughness, it is important to study the
corresponding bond strength under different bonding conditions. These results offer the required information for the process
design of copper wafer bonding in three-dimensional integration applications.
Journal of Electronic Materials 11/2005; 34(12):1464-1467. · 1.47 Impact Factor
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ABSTRACT: Silicon wafers are bonded using copper (Cu) as the bonding medium and annealed to enhance the bonding strength at temperatures ranging from 300 to 400 °C. The original bonding interface disappears and the Cu layers merge to form a single homogeneous layer. Cross-section transmission electron microscopy reveals a number of voids at the original bonding interface. It is observed that the size of these interfacial voids increases with bonding temperature. Thermal stress relaxation is proposed as the cause for interfacial void formation in the bonded Cu layers.
Applied Physics Letters 11/2005; 87(20):201909-201909-3. · 3.84 Impact Factor
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ABSTRACT: We have successfully demonstrated a back-to-face ultra-thin silicon layer stacking based on low temperature wafer bonding and etch-back. This type of silicon layer stacking can be expanded to wafers with device and interconnect layers to fabricate three-dimensional integrated circuits (3D ICs). Electrical connection between layers can be achieved by interlayer vertical via formed by bonded Cu layers.
SOI Conference, 2005. Proceedings. 2005 IEEE International; 11/2005
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ABSTRACT: Substrate noise is a major impediment to mixed-signal integration. This paper describes a CAD tool that can be used at any stage of the design cycle to estimate the substrate noise generated by large digital circuits. The results have been verified with substrate noise measurements on a 480 MHz digital PLL implemented in a 90 nm CMOS process on a high resistivity substrate.
Custom Integrated Circuits Conference, 2005. Proceedings of the IEEE 2005; 10/2005
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ABSTRACT: Process development of silicon layer stacking based on copper wafer bonding, grind-back, and etch-back was applied to demonstrate a strong four-layer-stack structure. Bonded copper layers in this structure became homogeneous layers and did not show original bonding interfaces. This process can be used in three-dimensional integrated circuit applications. Voids and total bonded area after each layer stacking were investigated for the bonding quality after each layer stacking. Large wafer bows from high residual stresses result in the structure failure at the stacking of a high number of layers.
Applied Physics Letters 07/2005; 87(3):031909-031909-3. · 3.84 Impact Factor
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ABSTRACT: This study characterizes the effect of substrate noise on a standard component of the RF front end: the voltage controlled oscillator (VCO), as well as evaluating the effect of VCO bias current and guard rings on noise performance. Frequency effects of substrate noise are also examined through the study of VCOs at three different center frequencies: 900 MHz, 2.4 GHz, and 5.2 GHz. Substrate noise is a serious problem that continues to plague mixed-signal designs. Components of the RF frontend are particularly sensitive to substrate noise as the effectiveness of standard isolation techniques degrades at higher frequencies. This study has shown that the phase noise of a VCO is adversely affected by substrate noise. In the extreme, the VCO can lock to the substrate noise. Guard rings can effectively attenuate substrate noise at lower frequencies. For example, at 900 MHz, as much as 25 dB of isolation is observed. At 5.2 GHz, the isolation reduces to 10 dB. Furthermore, the use of guard rings can improve the response of the VCO to injection locking.
Radio Frequency integrated Circuits (RFIC) Symposium, 2005. Digest of Papers. 2005 IEEE; 07/2005
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ABSTRACT: Using a combination of copper (Cu) thermocompression bonding and silicon wafer thinning, a face-to-face silicon bi-layer layer
stack is fabricated. The oxygen content in the bonded Cu layer is analyzed using secondary ion mass spectrometry (SIMS). Copper-covered
wafers that are exposed to the air for 12 h and 12 days prior to bonding exhibit 0.08 at.% and 2.96 at.% of oxygen, respectively.
However, prebonding forming gas anneal at 150°C for 15 min on 12-day-old Cu wafers successfully reduces the oxygen content
in the bonded Cu layer to 0.52 at.%.
Journal of Electronic Materials 01/2005; 34(12):1598-1602. · 1.47 Impact Factor
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ABSTRACT: Bonded copper interconnects were stressed with current to measure the specific contact resistance. For bonded copper interconnects without a prebonding HCl clean, the corresponding specific contact resistance did not change while increasing the stress current. However, for some interconnects with the prebonding HCl clean, an abnormal contact resistance reduction was observed during the increase of the stress current. The rise of temperature at the bonding interface area due to Joule heating under high current density may have caused the decrease of contact resistance. This behavior may be one option for quality enhancement in 3D integration at low temperature.
Applied Physics Letters 12/2004; 86(1):011903-011903-3. · 3.84 Impact Factor
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ABSTRACT: In this paper, we determine the accuracy of Rahman's interconnect prediction model for three-dimensional (3-D) integrated circuits. Utilizing this model, we calculate the wiring requirement for a set of benchmark standard-cell circuits. We then obtain placed and routed wirelength figures for these circuits using 3-D standard-cell placement and global-routing tools we have developed. We find that the Rahman model predicts wirelengths accurately (to within 20% of placement and of routing, on average), and suggest some areas for minor improvement to the model.
IEEE Transactions on Very Large Scale Integration (VLSI) Systems 05/2004; · 1.22 Impact Factor
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ABSTRACT: This paper analyzes the performance of different interconnect technologies for on-chip clock distribution, including conventional, three-dimensional, optical, and radio frequency interconnects. Skew, power, and area usage were estimated for each of these technologies based on the 2001 International Technology Roadmap for Semiconductors. Our results indicate that most of the skew and power are associated with local clock distribution. Consequently, since the alternative clock distribution approaches that have been proposed focus on global clock distribution, we have not found significant advantages over conventional clock distribution in terms of skew and power. Furthermore, it was found that low skews could be attained with conventional clock distribution schemes if the clock signals are not scaled down.
IEEE Transactions on Electron Devices 03/2004; · 2.32 Impact Factor
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ABSTRACT: A novel test structure for contact resistance measurement of bonded copper interconnects in three-dimensional integration technology is proposed and fabricated. This test structure requires a simple fabrication process and eliminates the possibility of measurement errors due to misalignment during bonding. Specific contact resistances of bonding interfaces with different interconnect sizes of approximately 10<sup>-8</sup> Ω-cm<sup>2</sup> are measured. A reduction in specific contact resistance is obtained by longer anneal time. The specific contact resistance of bonded interconnects with longer anneal time does not change with interconnect sizes.
IEEE Electron Device Letters 02/2004; · 2.85 Impact Factor
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ABSTRACT: Low-temperature direct plasma-enhanced chemical vapor deposition (PECVD) oxide to thermal oxide bonding is described. The PECVD oxide is densified at 350 °C and chemical-mechanically polished to obtain reasonably smooth surface for bonding. The PECVD oxide wafer is bonded to the thermal oxide wafer at room temperature after piranha clean that leaves the wafer surfaces hydrophilic. A postbonding anneal at 300 °C completes the bonding. A void-free bonding interface is observed from infrared imaging and the bonding strength is estimated to be 432 mJ/m2. This bonding method can be used in a variety of applications, including three-dimensional integration. © 2003 American Institute of Physics.
Applied Physics Letters 04/2003; 82(16):2649-2651. · 3.84 Impact Factor
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ABSTRACT: Three-dimensional integration technologies have been proposed in order to mitigate design challenges posed by deep-submicron interconnect. By providing multiple layers of active devices together with high-density local interconnects between these layers, 3-D technologies give digital-circuit designers greater freedom in meeting power and delay budgets that are increasingly interconnect-dominated. In this paper, we quantify the benefits 3-D integration can provide, using specific circuit benchmarks. We perform this analysis using a suite of circuit design tools we have developed for 3-D integration. We observe that on average, 28% to 51% reduction in total wire length is possible over two to five wafers respectively; similarly, 31% to 56% reduction in the length of the longest wire is achievable. We also characterize the impact of technology parameters on these reductions.
VLSI, 2003. Proceedings. IEEE Computer Society Annual Symposium on; 03/2003
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ABSTRACT: In this paper, analytical models for predicting interconnect requirements in field-programmable gate arrays (FPGAs) are presented, and opportunities for three-dimensional (3-D) implementation of FPGAs are examined. The analytical models for two-dimensional FPGAs are calibrated by routing and placement experiments with benchmark circuits and extended to 3-D FPGAs. Based on system-level modeling, we find that in FPGAs with more than 20 K four-input look-up tables, the reduction in channel width, interconnect delay and power dissipation can be over 50% by 3-D implementation.
IEEE Transactions on Very Large Scale Integration (VLSI) Systems 03/2003; · 1.22 Impact Factor
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ABSTRACT: We present a set of design tools for 3-D integration. Using these tools - a 3-D standard-cell placement tool, global routing tool, and layout editor - we have targeted existing standard-cell circuit netlists for fabrication using wafer bonding. We have analyzed the performance of several circuits using these tools and find that 3-D integration provides significant benefits. For example, relative to single-die placement, we observe on average 28% to 51% reduction in total wire length.
Design Automation Conference, 2003. Proceedings of the ASP-DAC 2003. Asia and South Pacific; 02/2003
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ABSTRACT: Interfacial morphologies during Cu wafer bonding at bonding temperatures of 300–400°C for 30 min followed by an optional 30-min
or 60-min nitrogen anneal were investigated by means of transmission electron microscopy (TEM). Results showed that increased
bonding temperature or increased annealing duration improved the bonding quality. Wafers bonded at 400°C for 30 min followed
by nitrogen annealing at 400°C for 30 min, and wafers bonded at 350°C for 30 min followed by nitrogen annealing at 350°C for
60 min achieve the same excellent bonding quality.
Journal of Electronic Materials 01/2003; 32(12):1371-1374. · 1.47 Impact Factor
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ABSTRACT: Evolution of microstructure morphologies and grain orientations of Cu–Cu bonded wafers during bonding and annealing were studied by means of transmission electron microscopy, electron diffraction, and x-ray diffraction. The bonded Cu grain structure reaches steady state after post-bonding anneal. An abnormal (220) grain growth was observed during the initial bonding process. Upon annealing, the preferred grain orientation of the whole film shifts from (111) to (220). The effects of yielding and energy minimization are possible reasons for the evolution of the preferred grain orientation. © 2002 American Institute of Physics.
Applied Physics Letters 11/2002; 81(20):3774-3776. · 3.84 Impact Factor
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ABSTRACT: The microstructure morphologies of copper bonded wafers were examined by means of transmission electron microscopy (TEM) and atomic force microscope (AFM). Morphologies of non-distinct, zigzag and distinct interfaces in the bonded layer are observed. A strong relationship between the roughness of surfaces and the individual steps in bonding initiation was found. We propose three different mechanisms to explain the observed morphologies. In addition, the role of atomic diffusion and that of annealing effects during bonding is discussed.
Journal of Materials Science 07/2002; 37(16):3441-3446. · 2.02 Impact Factor
