A. Vayshenker

Autonomous University of Barcelona, Cerdanyola del Vallès, Catalonia, Spain

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Publications (23)12.46 Total impact

  • A. Kerber, A. Vayshenker, D. Lipp, T. Nigam, E. Cartier
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    ABSTRACT: The root cause for the increase in the TDDB voltage acceleration with decreasing stress voltage in metal gate/high-k n-channel FETs is investigated. Using DC and AC stress methodologies, the effect could be linked to charge trapping in the high-k gate dielectric. Furthermore, a correction for charge trapping is proposed, which results in a single power law voltage dependence for all stress conditions.
    Reliability Physics Symposium (IRPS), 2010 IEEE International; 01/2010
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    ABSTRACT: An aggressively scaled high performance 45 nm bulk CMOS technology targeting graphic, gaming, wireless and digital home applications is presented. Through innovative utilization and integration of advanced stressors, thermal processes and other technology elements, at aggressively scaled 45 nm design ground rules, core NFET and PFET realized world leading drive currents of 1150 and 785 uA/um at 100 nA/um off current at IV, respectively. In addition to the high performance transistors, an ultra low-k back-end dielectric (k=2.4) significantly lowers wiring delay. In this technology, CMOS transistors with multiple-oxide thicknesses are supported for low leakage and I/O operations, and competitive SRAM is offered.
    VLSI Technology, 2007 IEEE Symposium on; 07/2007
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    ABSTRACT: Gate-first integration of band-edge (BE) high-κ/metal gate nFET devices with dual stress liners and silicon-on-insulator substrates for the 45nm node and beyond is presented. We show the first reported demonstration of improved short channel control with high-κ/metal gates (HK/MG) enabled by the thinnest T<sub>inv</sub> (≪12Å) for BE nFET devices to-date, consistent with simulations showing the need for ≪14Å T inv at Lgate≪35nm. We report the highest BE HK/MG nFET Idsat values at 1.0V operation. We also show for the first time BE high-κ/metal gate pFET's fabricated with gate-first high thermal budget processing with thin T<sub>inv</sub> (≪13Å) and low Vts appropriate for pFET devices. The reliability in these devices was found to be consistent with technology requirements. Integration of high-κ/metal gate nFET's into CMOS devices yielded large SRAM arrays.
    VLSI Technology, 2007 IEEE Symposium on; 07/2007
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    ABSTRACT: We present a 45-nm SOI CMOS technology that features: i) aggressive ground-rule (GR) scaling enabled by 1.2NA/193nm immersion lithography, ii) high-performance FET response enabled by the integration of multiple advanced strain and activation techniques, iii) a functional SRAM with cell size of 0.37mum<sup>2</sup>, and iv) a porous low-k (k=2.4) dielectric for minimized back-end wiring delay. The list of FET-specific performance elements includes enhanced dual-stress liner (DSL), advanced eSiGe, stress memorization (SMT), and advanced anneal (AA). The resulting PFET/NFET Idsat values, at Vdd of 1.0V and 45nm GR gate pitch, are 840muA/mum and 1240muA/mum respectively. The global wiring delay achieved with k=2.4 reflects a 20% reduction compared to k=3.0
    Electron Devices Meeting, 2006. IEDM '06. International; 01/2007
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    ABSTRACT: This paper presents a 65nm low power technology offering a dual gate oxide process, multiple Vt devices at a nominal operating voltage of 1.2V, a nine level hierarchical Cu interconnect back-end of line process with low k dielectrics and 0.676mum<sup>2</sup> and 0.54mum <sup>2</sup> SRAM cells, optimized for performance and density, respectively. The key focus of this technology has been low cost, process simplicity and power reduction. A gate dielectric with an nfet leakage current as low as 15pA/mum and with exceptional reliability characteristics has been demonstrated. Moreover, competitive drive current has been achieved, 725/343muA/mum at an off current of 7nA/mum for n/pfets at nominal voltage. A pfet performance enhancement of an additional 13% at 7nA/mum off current was achieved by using mobility enhancement techniques without adding process complexity. An optimized NiSi process and high angle, low dose halo implants contribute to the reduced junction leakage and GIDL current
    Electron Devices Meeting, 2005. IEDM Technical Digest. IEEE International; 01/2006
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    E. Wu, J. Sune, W. Lai, A. Vayshenker, D. Harmon
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    ABSTRACT: Breakdown (BD) characteristics and electron transport across thin SiO<sub>2</sub> films has been thoroughly investigated for P+Poly-Si gate/PFET devices stressed under inversion mode. We resolve the anomalies in T<sub>BD</sub>/Q<sub>BD</sub> polarity dependence and shallower Weibull slopes commonly observed in PFET for T<sub>OX</sub>>2nm. For thin oxides (1.8nm<T<sub>OX</sub><2.9nm), Q<sub>BD</sub> data and Weibull slopes are found to be in excellent agreement with those of NFETs by considering valence-band electron tunneling. For ultra-thin oxides (T <sub>OX</sub><1.8nm), using an improved new BD detection methodology, the derived Q<sub>BD</sub> results show reasonable agreement with those of thick oxides
    Electron Devices Meeting, 2005. IEDM Technical Digest. IEEE International; 01/2006
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    ABSTRACT: This paper reports a cutting-edge 65nm CMOS technology featuring high performance and low power CMOS devices for both general and low power applications. Utilizing plasma nitrided gate oxide, off-set and slim spacers, advanced co-implants, NiSi and low temperature MOL process, well designed NMOSFET and PMOSFET achieved significant improvement from the previous generation, especially PMOSFET has demonstrated an astonishing 35 % performance enhancement from the previous technology node
    Electron Devices Meeting, 2004. IEDM Technical Digest. IEEE International; 02/2004
  • Microelectronics Reliability. 01/2003; 43:1175-1184.
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    ABSTRACT: The limitations of silicon dioxide dielectric reliability for future CMOS scaling are investigated. Several critical aspects are examined, and new experimental results are used to form an empirical approach to a theoretical framework upon which the data is then interpreted. Experimental data over a wide range of oxide thickness, voltage, and temperature were gathered using structures with a wide range of gate-oxide areas, and over very long stress times. Resolution of seemingly contradictory observations regarding the temperature dependence of oxide breakdown is provided by this work. On the basis of these results, a unified, global picture of oxide breakdown is constructed and the resulting model is applied to project reliability limits for the wear-out of silicon dioxide. It is concluded that silicon dioxide-based dielectrics can provide reliable gate dielectric, even to a thickness of 1 nm, and that CMOS scaling may well be viable to the 50 nm technology node using silicon-dioxide-based gate insulators.
    Microelectronics Reliability 01/2003; · 1.14 Impact Factor
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    ABSTRACT: In this paper, we present experimental evidence on the voltage-dependence of the voltage acceleration factors observed on ultrathin oxides from 5 nm down to ∼1 nm over a wide range of voltages from ∼2 V to 6 V. Two independent experimental approaches, area scaling method and long-term stress, are used to investigate this phenomenon. We show the exponential law with a constant voltage-acceleration factor violates the widely accepted fundamental breakdown property of Poisson random statistics while the voltage-dependent voltage acceleration described by an empirical power-law relation preserves this well-known property. The apparent thickness-dependence of voltage acceleration factors measured in different voltage ranges can be nicely understood and unified with these independent experimental results in the scenario of a voltage-driven breakdown. In the framework of the critical defect density and defect generation rate for charge-to-breakdown, we explore the possible explanation of increasing voltage acceleration factors at reduced voltage by assuming a geometric model for the critical defect density.
    IEEE Transactions on Electron Devices 01/2003; · 2.06 Impact Factor
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    ABSTRACT: Hard breakdown is shown to be a gradual process with the gate current increasing at a predictable rate, exponentially dependent on the instantaneous stress voltage. Adding the hard breakdown evolution time to the standard time to breakdown potentially reduces the projected fail rate of gate dielectrics by orders of magnitude. The scaling of the hard breakdown growth rate with respect to device area, substrate doping, oxide thickness, and channel length are explored. A two-voltage stress procedure is introduced that measures degradation rates on sub-micron devices several orders of magnitude more quickly than a conventional single voltage stress.
    Reliability Physics Symposium Proceedings, 2003. 41st Annual. 2003 IEEE International; 01/2003
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    ABSTRACT: Hard breakdown (HBD) is shown to be a gradual process with the gate current increasing at a predictable rate exponentially dependent on the instantaneous stress voltage and oxide thickness. This is contrary to conventional wisdom that maintains that HBD is a fast thermally driven process. The HBD degradation rate (DR) for a 15 /spl Aring/ oxide scales from >1 mA/s at 4 V to <1 nA/s at 2 V, extrapolating to <10 fA/s at use voltage. Adding the HBD evolution time to the standard time-to-breakdown potentially reduces the projected fail rate of gate dielectrics by orders of magnitude.
    IEEE Electron Device Letters 12/2002; · 2.79 Impact Factor
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    ABSTRACT: In this work, we resolved several seemingly conflicting experimental observations regarding temperature dependence of oxide breakdown in the context of change of voltage acceleration factors with reducing voltages. It is found that voltage acceleration factor is temperature dependent at a fixed voltage while voltage acceleration factors are temperature independent at a fixed TBD. We unequivocally demonstrated that strong temperature dependence of time(charge)-to-breakdown, TBD(QBD), observed on ultra-thin gate oxides (<5 nm) is not a thickness effect as previously suggested. It is a consequence of two experimental facts: (1) voltage-dependent voltage acceleration and (2) temperature-independent voltage acceleration at a fixed TBD window. For the first time, time-to-breakdown at low temperature of −50 °C is reported. It is found that Weibull slopes are insensitive to temperature variations using accurate area-scaling method. The stress-induced leakage current (SILC) was used as a measure of defect-generation rate and critical defect density to investigate its correlation with the directly measured breakdown data, QBD(TBD). The comprehensive and statistical measurements of SILC at breakdown as a function of temperature are presented in detail for the first time. Based on these results, we conclude that SILC-based measurements cannot adequately explain the temperature dependence of oxide breakdown. Finally, we provide a global picture for time-to-breakdown in voltage and temperature domains constructed from two important empirical relations based on comprehensive experimental database.
    Solid-State Electronics 11/2002; · 1.48 Impact Factor
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    ABSTRACT: The limitations of reliability of silicon dioxide dielectric for future CMOS scaling are investigated. Several critical aspects are examined, and new experimental results are used to form an empirical approach to a theoretical framework upon which the data is interpreted. Experimental data over a wide range of oxide thickness (T OX ), voltage, and temperature were gathered using structures with a wide range of gate-oxide areas, and over very long stress times. This work resolves seemingly contradictory observations regarding the temperature dependence of oxide breakdown. On the basis of these results, a unified, global picture of oxide breakdown is constructed, and the resulting model is applied to project reliability limits for the wear-out of silicon dioxide. It is concluded that silicon-dioxide-based materials can provide a reliable gate dielectric, even to a thickness of 1 nm, and that CMOS scaling may well be viable to the 50-nm-technology node using silicon-dioxide-based gate insulat ors.
    Ibm Journal of Research and Development 04/2002; · 0.69 Impact Factor
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    ABSTRACT: This paper presents a high performance 90 nm generation SOI CMOS logic technology. Leveraging unique SOI technology features, aggressive ground rules and a tungsten local interconnect rendered the smallest 6T SRAM cell reported to date with a cell area of 0.992 /spl mu/m/sup 2/. In the front-end of line (FEOL), the implementation of super-halo design concepts on SOI substrates with a silicon thickness of 45 nm and an ultra-thin heavily nitrided gate dielectric resulted in highest performance devices. The backend of the line (BEOL) for this technology consists of damascene local interconnect followed by up to 10 levels of hierarchical Cu metallization. It utilizes SiLK/spl trade/ low-K dielectric material with a multilayer hard mask stack.
    Electron Devices Meeting, 2002. IEDM '02. International; 02/2002
  • E.Y. Wu, J.M. McKenna, W. Lai, E. Nowak, A. Vayshenker
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    ABSTRACT: We report the effect of change of voltage acceleration on temperature dependence of oxide breakdown for ultra-thin oxides below 6 nm. The time- or charge-to-breakdown (T/sub BD//Q/sub BD/) is directly measured over a wide range of temperatures (-30/spl deg/C to 200/spl deg/C) for several fixed voltages using different area capacitors and long-term stress. Using extensive experimental evidence, we unequivocally demonstrate that this strong temperature dependence of oxide breakdown on ultra-thin oxides is not a thickness effect as previously suggested at least for thickness range investigated in this work. It is a consequence of two experimental facts: 1) voltage-dependent voltage acceleration and 2) temperature-independent voltage acceleration within a fixed T/sub BD/ window. These results provide a coherent picture for T/sub BD/ in both voltage and temperature domains for ultra-thin oxides.
    IEEE Electron Device Letters 01/2002; · 2.79 Impact Factor
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    ABSTRACT: In this paper, we critically examine several important experimental aspects concerning ultrathin oxide reliability. The statistical nature of breakdown measurements and the impact on data interpretation is discussed. Thickness dependence of Weibull slopes and its impact on reliability projection is reviewed. We also investigate the voltage-dependent voltage acceleration using two independent experimental methods over a wide range of oxide thickness values. Within the framework of a general defect generation model, we explore the possibility of a voltage-dependent defect generation rate to account for the increase in voltage acceleration with decreasing voltages. Using direct experimental results, we clarify that strong temperature dependence found on ultrathin oxides is a voltage effect, not a thickness effect as previously suggested, In the context of voltage-dependent voltage acceleration, we experimentally resolve various seemingly contradicting and confusing observations such as temperature-independent voltage acceleration and non-Arrhenius temperature dependence found on ultrathin oxides. Finally, we provide a global picture for time-to-breakdown in voltage and temperature domain constructed from two important empirical principles based on comprehensive experimental database
    IEEE Transactions on Device and Materials Reliability 04/2001; · 1.52 Impact Factor
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    ABSTRACT: This paper describes a second generation 1.2 V high performance 0.13 μm SOI technology. Aggressive ground rules and a tungsten damascene local interconnect render the densest 6T 0.13 μm SRAM reported to date with a cell area of 1.80 μm<sup>2</sup>. 248 nm lithography is used for all critical levels. Interconnect performance requirements are achieved by using up to 8 levels of Cu wiring and an advanced BEOL process with low-k interlevel dielectrics and SiC barrier layers
    Electron Devices Meeting, 2001. IEDM Technical Digest. International; 02/2001
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    ABSTRACT: In this work, we unequivocally demonstrate that strong temperature dependence of time(charge)-to-breakdown TBD/QBD observed on ultra-thin oxides is not a thickness effect but rather a consequence of two experimental facts: (1) voltage-dependent voltage acceleration and (2) temperature-independent voltage acceleration within a fixed TBD window. By extending down to −30°C, we found non-Arrhenius temperature dependence is a totally independent effect. Based on our statistically accurate experimental database, we found that defect-generation rate and critical defect density as commonly measured using stress-induced leakage current (SILC) only show a change of two orders of magnitude and no change, respectively. Weibull slopes are also found to be temperature-independent. We propose an alternative model of two-step hydrogen degradation to explain these experimental results.
    Microelectronic Engineering. 01/2001;
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    ABSTRACT: We report the voltage-dependence of voltage acceleration for ultra-thin oxides from 2.2 V to 5 V over a range of T<sub>ox</sub> values from 1.7 nm to 5.0 nm. This unique behavior manifest itself as a power-law voltage-dependence for time-to-breakdown (T<sub>BD</sub>) over a variety of experimental observations. Using the concept of energy-to-breakdown, we explore the possible scenarios such as fractional energy or defect generation probability as a function of voltage to account for the increase in voltage acceleration with decreasing voltages
    Electron Devices Meeting, 2000. IEDM Technical Digest. International; 02/2000