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ABSTRACT: An interpolative-phase-tuning (IPT) technique is proposed to tune the frequency of millimeter-wave (MMW) LC-based ring oscillators without using varactor. As a key feature, the tradeoff between tank Q and tuning range of the proposed IPT oscillators is independent of the operation frequency, which makes the IPT technique suitable for applications at MMW frequencies. Moreover, the IPT oscillators can achieve larger frequency tuning range and much better phase accuracy over the tuning range as compared to the conventional gm-coupled LC oscillators for multiphase generation. Two IPT oscillator prototypes are designed and implemented in a 0.13-μm CMOS process. The first one operates at 50 GHz with eight output phases and measures phase noise of -103.7 dBc/Hz at 1-MHz offset and -127.8 dBc/Hz at 10-MHz offset, tuning range of 6.8%, and figure of merit (FOM) of 186.4 dB while occupying chip area of 0.36 mm<sup>2</sup>. The second prototype oscillates at 60 GHz with four output phases and measures phase noise of -95.5 dBc/Hz at 1-MHz offset, -120.6 dBc/Hz at 10-MHz offset, tuning range of 9%, and FOM of 180.6 dB with chip area of 0.2 mm<sup>2</sup>.
IEEE Journal of Solid-State Circuits 09/2011; · 3.23 Impact Factor
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ABSTRACT: Extensive research has been focused on generating LO signals for software-defined radios (SDRs) with ultra-wide tuning range over several frequency decades and sufficiently high spectrum purity to support diverse wireless standards. This work presents an integrated frequency synthesizer (FS) that is able to cover not only all the wireless standards from 47 MHz to 10 GHz including 14-band MB-OFDM UWB but also the 802.15.3c standard from 57 to 66 GHz.
Solid-State Circuits Conference Digest of Technical Papers (ISSCC), 2011 IEEE International; 03/2011
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ABSTRACT: An interpolative-phase-tuning technique is presented to tune the frequency of millimeter-wave LC-based ring oscillators without using varactors. Two oscillator prototypes are designed and implemented in a 0.13-μm CMOS process. The first oscillator operates at 50GHz with 8 output phases and measures phase noise of -127.8dBc/Hz at 10MHz offset, tuning range of 6.8%, and figure of merit (FOM) of 186.4dB while occupying chip area of 0.36mm<sup>2</sup>. The second prototype oscillates at 60GHz with 4 output phases and measures phase noise of -120.6dBc/Hz at 10MHz offset, tuning range of 9%, and FOM of 180.6dB with chip area of 0.2mm<sup>2</sup>.
Custom Integrated Circuits Conference (CICC), 2010 IEEE; 10/2010
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ABSTRACT: By exploiting the intrinsic multiple oscillation modes of a standing-wave oscillator, a dual-band millimeter-wave VCO is designed. Implemented in 0.13μm CMOS with an area of 0.05mm<sup>2</sup>, the VCO prototype measures a dual-band operation at 24 GHz and 60 GHz with tuning range of 10.8% and 7.2%, phase noise of -120dBc/Hz and -114dBc/Hz at 10MHz offset, power consumption of 11mW and 24mW, corresponding to FoM of -177dB and -176dB, respectively.
Radio Frequency Integrated Circuits Symposium (RFIC), 2010 IEEE; 06/2010
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ABSTRACT: Frequency dividers are key components for frequency synthesis in wireless and wireline communication systems. Among different types of frequency dividers, LC-based injection-locked frequency dividers (ILFDs) feature high- frequency operation at low power consumption, but their locking range is quite narrow due to the high-Q nature of the resonator. Recently, design techniques to enhance the locking range of ILFDs have been reported. Injection into two coupled LC oscillators and sandwiched injection into two identical LC oscillators are proposed, but these techniques are suitable for dividers with quadrature outputs. Inductive-peaking and transconductance enhancement techniques are also used but they require extra inductors and thus larger chip area. In this paper, a simple but effective technique is presented to improve the locking range of ILFDs without extra inductive components while consuming low power.
Solid-State Circuits Conference - Digest of Technical Papers, 2009. ISSCC 2009. IEEE International; 03/2009
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ABSTRACT: This paper presents the design and integration of a fully-integrated dual-conversion zero-IF2 CMOS transceiver for 9-band MB-OFDM UWB systems from 3.1 GHz to 8.0 GHz. The transceiver integrates all building blocks including a variable-gain wideband LNA, a single combined mixer for both RF down-conversion in RX and up-conversion in TX, a fast-settling frequency synthesizer, and IQ ADCs and DACs. Fabricated in a standard 0.18- mum CMOS process, the receiver measures maximum S11 of - 13 dB, maximum NF of 8.25 dB, in-band IIP3 of better than -13.7 dBm, and variable gain from 25.3 to 84.0 dB. IQ path gain and phase mismatches of the receiver chain are measured to be 0.8 dB and 4 <sup>deg</sup>, respectively. The transmitter achieves a minimum output P-1 dB of -8.2 dBm, sideband rejection of better than -42.2 dBc, and LO leakage of smaller than - 46.5 dBc.
IEEE Journal of Solid-State Circuits 03/2009; · 3.23 Impact Factor
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ABSTRACT: This paper presents the design and analysis of a proposed double-balanced quadrature-input quadrature-output (QIQO) regenerative divider for ultra-wideband (UWB) synthesizer applications. By fully utilizing the quadrature phase outputs already existed in a quadrature voltage-controlled oscillator (QVCO) or any other quadrature signal generator (QSG), the proposed QIQO divider provides a mechanism to achieve an output IQ phase sequence that is inherently tracked with the input IQ phase sequence. Moreover, compared with conventional dividers, the QIQO divider provides not only smaller and better-matched input loading to the QSG but also improved quadrature phase accuracy, wider operation range, smaller third harmonics, and lower power consumption. Fabricated in a 0.18-mum CMOS process, the QIQO divider measures an image rejection of -62dBc with a frequency operation range of larger than 18.4% from 8.6 GHz to 10.34 GHz while consuming 7.2 mW at 0.9-V supply.
Circuits and Systems I: Regular Papers, IEEE Transactions on 11/2008; · 1.97 Impact Factor
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ABSTRACT: This paper presents the design and analysis of ultra- low-voltage (ULV) high-frequency dividers using transformer feedback. Specifically, a differential-input differential-output injection-locked (IL) divider topology with transformer feedback and a wideband transformer-coupled (TC) divider with quadrature outputs are demonstrated, both of which can operate well at supply voltages as low as the device's threshold voltages. Fabricated in a standard 0.18-mum CMOS process, the ULV-IL divider measures an input frequency range from 16.1 GHz to 20 GHz while consuming a total power from 2.75 mW to 4.35 mW at 0.5 V supply, and the TC-divider measures an input frequency range of 27.8% from 15.1 GHz to 20 GHz with IQ sideband rejection of - 31 dBc while consuming power from 11.4 mW to 13.6 mW at 0.6 V supply.
IEEE Journal of Solid-State Circuits 11/2008; · 3.23 Impact Factor
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ABSTRACT: An ultra-wideband low-noise amplifier (LNA) is designed for software-defined radios (SDR). Noise-cancellation common-gate stage is combined with capacitive cross coupling for wideband input impedance matching and small noise figure (NF). T-coils and inductive peaking are employed to extend the output bandwidth and to reject the noise from the loading resistors. Linearization using second-order intermodulation injection is adopted to improve the IIP<sub>3</sub>. Operated at 1.5 V from 0.8 GHz to 10.6 GHz, the 0.13-mum CMOS LNA measures 16-dB gain, -12 dB S<sub>11</sub>, 3.4-5.6 dB NF, and 1.6-dBm IIP<sub>3</sub>.
Custom Integrated Circuits Conference, 2008. CICC 2008. IEEE; 10/2008
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ABSTRACT: A new quadrature VCO is designed in a standard UMC 0.13 mu m CMOS process with low voltage, low power and low phase noise. Diodes are employed to generate second-harmonic coupling between the common sources of two LC VCOs for quadrature outputs. At 1-V supply and at 3.9 GHz, the QVCO measures phase noise of -117dBc/Hz at 1-MHz offset while dissipating 7.5 mA which corresponds to a figure of merit of 180 dBc. The core area is 0.37 mm<sup>2</sup>.
Radio and Wireless Symposium, 2008 IEEE; 02/2008
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ABSTRACT: A 1-V CMOS frequency synthesizer is proposed for wireless local area network 802.11a transceivers using a novel transformer-feedback voltage-controlled oscillator (VCO) for low voltage and a stacked frequency divider for low power. Implemented in a 0.18-mum CMOS process and operated at 1-V supply, the VCO measures a phase noise of -140.5 dBc at an offset of 20 MHz with a center frequency of 4.26 GHz and a power consumption of 5.17 mW. Its tuning range is as wide as 920 MHz (23%). By integrating the VCO into a frequency synthesizer, a phase noise of -140.1 dBc/Hz at an offset of 20 MHz is measured at a center frequency of 4.26 GHz. Its output frequency can be changed from 4.112 to 4.352 GHz by switching the 3-bit modulus of the programmable divider. The synthesizer consumes only 9.7 mW and occupies a chip area of 1.28 mm<sup>2</sup>.
IEEE Transactions on Microwave Theory and Techniques 02/2008; · 1.85 Impact Factor
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ABSTRACT: This paper presents the design of an ultra-low-voltage (ULV) transformer-coupled (TC) frequency divider. On-chip transformers are used to cross-couple two regenerative dividers for quadrature-phase generation while achieving low-voltage, low-power and wideband operation. Implemented in a standard 0.13-mum CMOS process, the ULV-TC divider measures an input operation range of 19.2% from 22.6 GHz to 27.4 GHz and an IQ sideband rejection of 41 dB while consuming a minimum 6.8 mW from a 0.55 V power supply.
Solid-State Circuits Conference, 2007. ASSCC '07. IEEE Asian; 12/2007
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ABSTRACT: A new concept for quadrature coupling of LC oscillators is introduced and demonstrated in a 4.5-GHz CMOS quadrature voltage-controlled oscillator (QVCO). By employing cupacitivc coupling of second harmonic components, quadrature outputs can be obtained at a low supply voltage without extra power consumption. Fabricated in a 0.13 mum CMOS process and operated at 0.8-V supply, the proposed QVCO measures phase noise of-112dBc/Hz at 1M offset from -1.91GHz while drawing a total current of 4mA, which corresponds to a FOM of 181 dB. The core area is 0.278mm<sup>2</sup>.
Solid-State Circuits Conference, 2007. ASSCC '07. IEEE Asian; 12/2007
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ABSTRACT: A transformer-feedback injection-locked divide-by-3 frequency divider (ILFD) is proposed. Employing a transformer feedback, the divider can achieve high performance in terms of low voltage, high frequency, and low power consumption. Fabricated in a 0.13-mum CMOS process and operated at a 1-V supply voltage, the divider prototype measures an input frequency range from 22.7 GHz to 25.1 GHz with 2<sup>nd</sup> and 3<sup>rd</sup> harmonic tones of -45 dBc and -40 dBc respectively. With quadrature outputs, the divider achieves a sideband rejection ratio of 40 dB while consuming 1.7 mW and occupying an active area of 0.23 mm<sup>2</sup>.
Solid-State Circuits Conference, 2007. ASSCC '07. IEEE Asian; 12/2007
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ABSTRACT: A linearization technique is proposed in which low-frequency 2<sup>nd</sup>-order intermodulation IM2 is injected to suppress the 3<sup>rd</sup>-order intermodulation IM3. The proposed linearization technique is applied to both an LNA and a down-conversion mixer in an RF receiver front-end (RFE) working at 900-MHz. Fabricated in a 0.18-mum CMOS process and operated at 1.5 V supply, the RFE delivers 22-dB gain with 5.3-dB noise figure (NF). The linearization technique measures around 20-dB IM3 suppression without gain reduction and noise penality, and with only extra current of 0.2 mA.
Solid-State Circuits Conference, 2007. ASSCC '07. IEEE Asian; 12/2007
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ABSTRACT: A notch-peak cancellation concept is introduced in transformer-based LC tanks to achieve a dual-band quadrature VCO. Fabricated in 0.18 μm CMOS process and operated at 1V supply, the QVCO prototype measures a stable dual-band operation from 3.27 GHz to 5.02 GHz and from 9.48 GHz to 11.36 GHz. At 4.2 GHz and 10 GHz, the QVCO measures phase noise at 1 MHz offset of -116.3 dBc/Hz and -112 dBc/Hz, and sideband rejection ratios (SBR) of 49 dB and 47 dB while drawing 6 mA and 10 mA, respectively. The QVCO occupies an active area of 0.88 mm<sup>2</sup>.
Custom Integrated Circuits Conference, 2007. CICC '07. IEEE; 10/2007
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ABSTRACT: An ultra-low-voltage (ULV) differential injection-locked (IL) divider topology is presented. By making use of a double-balanced active mixer with transformer feedback and a transformer-feedback VCO, the proposed ULV-IL divider features double-balanced differential-input differential-output, an ultra-low supply voltage comparable to the device threshold voltage, and low power consumption. Fabricated in a standard 0.18-μm CMOS process and operated at 0.5-V supply, the ULV-IL divider measures an input frequency range from 16.1 GHz to 20 GHz while consuming a total power from 2.75 mW to 4.35 mW. Moreover, two identical proposed ULV-IL dividers with differential inputs are implemented to achieve quadrature outputs with measured IQ sideband rejection of better than -35 dBc.
Custom Integrated Circuits Conference, 2007. CICC '07. IEEE; 10/2007
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ABSTRACT: This paper presents a complete CMOS dual-conversion zero-IF2 transceiver for 9-band MB-OFDM UWB systems from 3.1 to 8.0 GHz. The transceiver integrates all building blocks including a variable-gain wideband LNA, a single mixer for both RF down and up conversions in RX and TX, a fast-settling frequency synthesizer, and IQ ADCs and DACs. Fabricated in a standard 0.18-μm CMOS process, the receiver measures maximum Sll of -13dB, maximum NF of 8.25 dB, in-band IIP3 of better than -13.7 dBm, and variable gain from 25.3 to 84.0 dB. IQ path gain and phase mismatch of the receiver chain are measured to be 0.8 dB and 4deg respectively. The transmitter achieves a minimum output P-1dB of -8.2 dBm, sideband rejection of better than -42.2 dBc, and LO leakage of smaller than -46.5 dBc.
Custom Integrated Circuits Conference, 2007. CICC '07. IEEE; 10/2007
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W. Wang,
S. Lou,
K. Chui,
S. Rong,
C.F. Lok,
H. Zheng,
H.T. Chan,
S.W. Man, H.C. Luong,
V.K. Lau,
C.Y. Tsui
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ABSTRACT: An 860MHz-960 MHz UHF RFID reader is designed in 0.18- μm CMOS that fully integrates an RF transceiver and a digital baseband. Highly reconfigurable mixed-signal baseband architecture for channel-selection filtering is proposed to achieve optimal power consumption for multi-protocol operation with different system dynamic ranges and data rates. In the talk mode with LNA bypassed, the RX measures a sensitivity of 70 dBm in the presence of a 5 dBm self-interferer. In the listen mode, LNA is turned on, and RX sensitivity is 90 dBm is measured. The TX achieves output power from -9 to lldBm with output P-ldB of 10.4 dBm.
Custom Integrated Circuits Conference, 2007. CICC '07. IEEE; 10/2007
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ABSTRACT: An ultra-low-power clock generator for passive UHF RFID tag is implemented in 0.18-mum CMOS process. By using the technique of dual-path clock generation with multiple clock rates and multiple supply voltages, clock accuracy is much improved and power consumption is reduced. Under the injection-locked condition, the measured cycle-to-cycle jitter of the clock generator is 23.7 ps and the peak-to-peak value is 164 ps with an input at 900 MHz and an output at 3.5 MHz. The overall power consumption is only 7 muW and the core chip area is 0.02 mm<sup>2</sup>.
33rd European Solid State Circuits Conference, 2007. ESSCIRC; 10/2007
