[show abstract][hide abstract] ABSTRACT: A predictive MOSFET model is very critical for early circuit design in nanoscale CMOS technologies. In this work, we developed a new compact MOSFET model which can dramatically improve the predictability of BSIM4 for the major 3 process and 2 layout variations by applying the simple physics-based equations to model these parameters. The accuracy of the model is verified using numerical TCAD simulation results and measurements under full range of temperature and bias conditions. The compact model for the circuit simulation can be efficiently used to predict the effects of process and layout variations on the circuit characteristics.
Simulation of Semiconductor Processes and Devices (SISPAD), 2010 International Conference on; 10/2010
[show abstract][hide abstract] ABSTRACT: A unified compact model to predict the performance degradation of a circuit due to the electrical gate oxide stress is developed and verified by experimental results. Hot carrier injection (HCI), off-state (OS), and Fowler-Nordheim (FN) degradations can be described by a single formula which models the trap generation over the stress time and voltage. With the proposed model, the propagation delay (tPD) degradation of a ring oscillator is reproduced with the accuracy of more than 90%. It is found that OS plays major role in the tPD degradation rather than HCI, while the component ratio of HCI is getting larger as the frequency increases.
Electron Devices Meeting, 2007. IEDM 2007. IEEE International; 01/2008
[show abstract][hide abstract] ABSTRACT: A practical model for a single-electron transistor (SET) was developed based on the physical phenomena in realistic Si SETs, and implemented into a conventional circuit simulator. In the proposed model, the SET current calculated by the analytic model is combined with the parasitic MOSFET characteristics, which have been observed in many recently reported SETs formed on Si nanostructures. The SPICE simulation results were compared with the measured characteristics of the Si SETs. In terms of the bias, temperature, and size dependence of the realistic SET characteristics, an extensive comparison leads to good agreement within a reasonable level of accuracy. This result is noticeable in that a single set of model parameters was used, while considering divergent physical phenomena such as the parasitic MOSFET, the Coulomb oscillation phase shift, and the tunneling resistance modulated by the gate bias. When compared to the measured data, the accuracy of the voltage transfer characteristics of a single-electron inverter obtained from the SPICE simulation was within 15%. This new SPICE model can be applied to estimating the realistic performance of a CMOS/SET hybrid circuit or various SET logic architectures.
IEEE Transactions on Nanotechnology 01/2003; · 1.80 Impact Factor
[show abstract][hide abstract] ABSTRACT: An efficient modeling methodology for abnormally structured MOS transistors is presented. Contrary to the previous method utilizing a 3D device simulator, only the 3D Poisson solver is used to characterize the current degradation effects by extracting the parasitic source and drain resistances, and the effective transistor width of the abnormal transistors. For the frequent modifications of the layout design, the easiness of the proposed method guarantees the efficient reflection of the current degradation effect in circuit simulation. This method is applied to 0.17 μm DRAM process and the good agreements with the measured data are examined.
Quality Electronic Design, 2002. Proceedings. International Symposium on; 02/2002
[show abstract][hide abstract] ABSTRACT: This paper describes the S-TFT model developed for poly-Si TFT
which improves the accuracy dramatically. The proposed model emphasis is
on deriving the large parasitic resistance characteristics at low Vds by
adding the junction current to the on-current. The physical-based
subthreshold and off-state current model are also considered. The model
guarantees the continuities of the current and the derivatives. Compared
to the RPI model, known to be the best model, the proposed model
improved overall simulation speed by 40-50% due to the better
Custom Integrated Circuits Conference, 2000. CICC. Proceedings of the IEEE 2000; 02/2000